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Datasheet Microsemi A2F200M3F-FG256

Manufacturer:Microsemi
Family:SmartFusion
Series:A2F200
Part Number:A2F200M3F-FG256

SmartFusion System on Chip (SoC) FPGAs are the only devices that integrate an FPGA fabric, ARM Cortex-M3 Processor, and programmable analog circuitry, offering the benefits of full customization and IP protection, while still being easy to use. Based on a proprietary flash process, SmartFusion SoC FPGAs are ideal for hardware and embedded designers who need a true system-on-chip (SoC) solution that gives more flexibility than traditional fixed-function microcontrollers without the excessive cost of soft processor cores on traditional FPGAs.

Microcontroller Subsystem (MSS)

  • Hardware industry-standard 100 MHz, 32-bit ARM Cortex-M3 CPU
  • Multi-layer AHB communication matrix with up to 16 Gbps throughput
  • 10/100 Ethernet MAC with RMII interface
  • Two of each: SPI, I2C, UART, 32-bit timers
  • Up to 512 KB flash and 64 KB of SRAM
  • External memory controller (EMC)
  • 8-channel DMA controller
  • Up to 41 MSS I/Os with Schmitt trigger inputs
    • 25 I/Os can be used as FPGA I/Os

FPGA Fabric

  • Based on Microsemi’s proven ProASIC3 architecture
  • 60,000 to 500,000 system gates with 350 MHz system performance
  • Embedded SRAMs and FIFOs
    • Variable aspect ratio 4,608-bit SRAM blocks
    • x1, x2, x4, x9 and x18 organizations
    • True dual-port SRAM (including x18)
  • Up to 128 FPGA I/Os supporting LVDS, PCI, PCI-X and LVTTL/LVCMOS standards

Programmable Analog

  • High-performance analog signal conditioning blocks (SCB) with voltage, current and temperature monitors
  • Analog compute engine (ACE) offloads CPU from analog initialization and processing of analog-to-digital conversion (ADC), digital-to-analog conversion (DAC) and SCBs
  • Integrated ADCs and DACs with 1 percent accuracy
  • 12-/10-/8-bit mode ADCs with 500/550/600 Ksps sampling rate
  • Up to ten 15 ns high-speed comparators
  • Up to 32 analog inputs and 3 outputs
FPGA Fabric
A2F060
A2F200
A2F500
TQ144
CS288
FG256
PQ208
CS288
FG256
FG484
PQ208
CS288
FG256
FG484
System Gates
60,000
200,000
500,000
Tiles (D-Flip-Flops)
1,536
4,608
11,520
RAM Blocks (4,608 bits)
8
8
24
 
A2F060
A2F200
A2F500
Microcontroller Subsystem (MSS)
TQ144
CS288
FG256
PQ208
CS288
FG256
FG484
PQ208
CS288
FG256
FG484
Flash (Kbytes)
128
256
512
SRAM (Kbytes)
16
64
64
Cortex-M3 processor with MPU
Yes
Yes
Yes
10/100 Ethernet MAC
No
Yes
Yes
External Memory
Controller (EMC)
26- bit address /
16- bit data
26- bit address /
16- bit data
26- bit address /
16- bit data
DMA
8 Ch
8 Ch
8 Ch
I2C
2
2
2
SPI
1
2
1
2
1
2
16550 UART
2
2
2
32-Bit Timer
2
2
2
PLL
1
1
1
2
1
2
32 KHz Low-Power
Oscillator
1
1
1
100 MHz On-Chip RC
Oscillator
1
1
1
Main Oscillator (32 KHz to
20 MHz)
1
1
1
 
A2F060
A2F200
A2F500
Programmable Analog
TQ144
CS288
FG256
PQ208
CS288
FG256
FG484
PQ208
CS288
FG256
FG484
ADCs(8-/10-/12-bit SAR)
1
2
2
3
DACs (8-/16-/24-bit sigma-delta)
1
2
2
3
Signal Conditioning Blocks
(SCBs)
1
4
4
5
Comparators1
2
8
8
10
Current Monitors1
1
4
4
5
Temperature Monitors1
1
4
4
5
Bipolar High Voltage
Monitors1
2
8
8
10
Temperature Grade
C, I, M
C, I
C, I, M

Notes:

  1. These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in the SmartFusion Analog UG for details.

Datasheets

  • Download » Datasheet, PDF, 11.0 Mb
    Docket ↓
    Revision 12 SmartFusion Customizable System-on-Chip (cSoC)
    Microcontroller Subsystem (MSS) Hard 100 MHz 32-Bit ARM CortexTM-M3 1.25 DMIPS/MHz Throughput from Zero Wait State Memory Memory Protection Unit (MPU) Single Cycle Multiplication, Hardware Divide JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Single Wire Viewer (SWV) Interfaces Internal Memory Embedded Nonvolatile Flash Memory (eNVM), 128 Kbytes to 512 Kbytes Embedded High-Speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, Implemented in 2 Physical Blocks to Enable Simultaneous Access from 2 Different Masters Multi-Layer AHB Communications Matrix Provides up to 16 Gbps of On-Chip Memory Bandwidth,1 Allowing Multi-Master Schemes 10/100 Ethernet MAC with RMII Interface2 Programmable External Memory Controller, Which Supports: Asynchronous Memories NOR Flash, SRAM, PSRAM Synchronous SRAMs Two I2C Peripherals Two 16550 Compatible UARTs Two SPI Peripherals Two 32-Bit Timers 32-Bit Watchdog Timer 8-Channel DMA Controller to Offload the Cortex-M3 from Data Transactions Clock Sources 32 KHz to 20 MHz Main Oscillator Battery-Backed 32 KHz Low Power Oscillator with Real-Time Counter (RTC) 100 MHz Embedded RC Oscillator; 1% Accurate Embedded Analog PLL with 4 Output Phases (0, 90, 180, 270) Based on proven ProASIC3 FPGA Fabric Low Power, Firm-Error Immune 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Instant On, Retains Program When Powered Off 350 MHz System Performance Embedded SRAMs and FIFOs Variable Aspect Ratio 4,608-Bit SRAM Blocks x1, x2, x4, x9, and x18 Organizations True Dual-Port SRAM (excluding x18)
    Programmable Embedded FIFO Control Logic Secure ISP with 128-Bit AES via JTAG FlashLock to Secure FPGA Contents Five Clock Conditioning Circuits (CCCs) with up to 2 Integrated Analog PLLs Phase Shift, Multiply/Divide, and Delay Capabilities Frequency: Input 1.5350 MHz, Output 0.75 to 350 MHz Programmable Analog
    Analog Front-End (AFE) Up to Three 12-Bit SAR ADCs 500 Ksps in 12-Bit Mode 550 Ksps in 10-Bit Mode 600 Ksps in 8-Bit Mode Internal 2.56 V Reference or Optional External Reference One First-Order DAC (sigma-delta) per ADC 8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate Up to 5 High-Performance Analog Signal Conditioning Blocks (SCB) per Device, Each Including: Two High-Voltage Bipolar Voltage Monitors (with 4 input ranges from 2.5 V to 11.5/+14 V) with 1% Accuracy High Gain Current Monitor, Differential Gain = 50, up to 14 V Common Mode Temperature Monitor (Resolution = C in 12-Bit Mode; Accurate from 55C to 150 ...

Other Names: A2F200M3FFG256, A2F200M3F FG256

Docket:
Revision 12 SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS) Hard 100 MHz 32-Bit ARM CortexTM-M3 1.25 DMIPS/MHz Throughput from Zero Wait State Memory Memory Protection Unit (MPU) Single Cycle Multiplication, Hardware Divide JTAG Debug (4 wires), Serial Wire Debug (SWD, 2 wires), and Single Wire Viewer (SWV) Interfaces Internal Memory Embedded Nonvolatile Flash Memory (eNVM), 128 Kbytes to 512 Kbytes Embedded High-Speed SRAM (eSRAM), 16 Kbytes to 64 Kbytes, Implemented in 2 Physical Blocks to Enable Simultaneous Access from 2 Different Masters Multi-Layer AHB Communications Matrix Provides up to 16 Gbps of On-Chip Memory Bandwidth,1 Allowing Multi-Master Schemes 10/100 Ethernet MAC with RMII Interface2 Programmable External Memory Controller, Which Supports: Asynchronous Memories NOR Flash, SRAM, PSRAM Synchronous SRAMs Two I2C Peripherals Two 16550 Compatible UARTs Two SPI Peripherals Two 32-Bit Timers 32-Bit Watchdog Timer 8-Channel DMA Controller to Offload the Cortex-M3 from Data Transactions Clock Sources 32 KHz to 20 MHz Main Oscillator Battery-Backed 32 KHz Low Power Oscillator with Real-Time Counter (RTC) 100 MHz Embedded RC Oscillator; 1% Accurate Embedded Analog PLL with 4 Output Phases (0, 90, 180, 270) Based on proven ProASIC3 FPGA Fabric Low Power, Firm-Error Immune 130-nm, 7-Layer Metal, Flash-Based CMOS Process Nonvolatile, Instant On, Retains Program When Powered Off 350 MHz System Performance Embedded SRAMs and FIFOs Variable Aspect Ratio 4,608-Bit SRAM Blocks x1, x2, x4, x9, and x18 Organizations True Dual-Port SRAM (excluding x18)
Programmable Embedded F...

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