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Datasheet Efficient Power Conversion EPC2102ENG

Manufacturer:Efficient Power Conversion
Series:EPC2102
Part Number:EPC2102ENG

60 V Enhancement-Mode GaN Power Transistor Half Bridge

Datasheets

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    EPC2102 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
    Features: 98% System Efficiency at 18 A o o 42 VIN to 14 VOUT, 500 kHz Includes driver, inductor, and output filter High Frequency Operation High Density Footprint Low Inductance Package EPC2102 devices are supplied only in passivated die form with solder balls Die Size: 6.05 mm x 2.3 mm Pb-Free (RoHS Compliant), Halogen Free Applications: High Frequency DC-DC Conversion
    99 Typical System Efficiency Typical Circuit
    Efficiency (%) 98.5 98 97.5 97 96.5 96 95.5 95 0 2 4 6 8 10 12 14 16 18 20 22 24 26 fsw=300 kHz fsw=500 kHz Output Current (A) VIN = 42 V, VOUT = 14 V MAXIMUM RATINGS Parameter
    Maximum Drain Source Voltage (VSW to PGND, VIN to VSW) Maximum Gate Source Voltage Range (Gate 1 to VSW, Gate 2 to PGND) Continuous Drain Current, 25 C, RJA = 28 (Q1), 28 (Q2) Maximum Pulsed Drain Current, 25 C, Tpulse = 300 s Optimum Temperature Range Q1 Control FET Q2 Sync FET Q1 Control FET Q2 Sync FET Value
    60 V -4 V < VGS < 6 V 23 A 23 A 215 A 215 A -40 C < TJ < 150 C Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 1 EPC2102 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
    STATIC CHARACTERISTICS Parameter
    Maximum Drain Source Voltage (BVDSS) Maximum Drain Source Leakage Maximum RDS(on) Typical RDS(on) Gate Source Threshold Voltage Gate Source Maximum Positive Leakage Gate Source Maximum Negative Leakage
    TJ = 25 C unless otherwise stated Conditions
    Q1: VGS = 0 V, ID = 430 A Q2: VGS = 0 V, ID = 430 A VDS = 48 V, VGS = 0 V VGS = 5 V, ID = 20 A VGS = 5 V, ID = 20 A Q1: ID = 7 mA, VDS = VGS Q2: ID = 7 mA, VDS = VGS VGS = 5 V VGS = -4 V Q1 Control FET Q2 Sync FET
    60 V 360 A 4.4 m 3.2 m 360 A 4.4 m 3.2 m 0.8 V < VGS(TH) < 2.5 V 7 mA -360 A 7 mA -360 A DYNAMIC CHARACTERISTICS Parameter
    CISS (Input Capacitance) COSS (Output Capacitance) CRSS (Reverse Transfer Capacitance) QG (Total Gate Charge) QGS (Gate to Source Charge) QGD (Gate to Drain Charge) QG(TH) (Gate Charge at Threshold) QOSS (Output Charge) QRR (Source-Drain Recovery Charge)
    TJ = 25 C unless otherwise stated Conditions
    VDS = 30 V, VGS = 0 V
    VDS = 30 V, ID = 20 A, VGS = 5 V Typical Value Q1 Control FET Q2 Sync FET Unit
    0.83 0.51 0.014 6.8 2.3 1.4 1.8 23 0 0.83 0.71 0.014 6.8 2.3 1.4 1.8 31 0 nC nF VDS = 30 V, ID = 20 A VDS = 30 V, VGS = 0 V Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 2 EPC2102 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
    THERMAL CHARACTERISTICS TYP Q1 Control FET ...

Prices

Docket:
EPC2102 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
Features: 98% System Efficiency at 18 A o o 42 VIN to 14 VOUT, 500 kHz Includes driver, inductor, and output filter High Frequency Operation High Density Footprint Low Inductance Package EPC2102 devices are supplied only in passivated die form with solder balls Die Size: 6.05 mm x 2.3 mm Pb-Free (RoHS Compliant), Halogen Free Applications: High Frequency DC-DC Conversion
99 Typical System Efficiency Typical Circuit
Efficiency (%) 98.5 98 97.5 97 96.5 96 95.5 95 0 2 4 6 8 10 12 14 16 18 20 22 24 26 fsw=300 kHz fsw=500 kHz Output Current (A) VIN = 42 V, VOUT = 14 V MAXIMUM RATINGS Parameter
Maximum Drain Source Voltage (VSW to PGND, VIN to VSW) Maximum Gate Source Voltage Range (Gate 1 to VSW, Gate 2 to PGND) Continuous Drain Current, 25 C, RJA = 28 (Q1), 28 (Q2) Maximum Pulsed Drain Current, 25 C, Tpulse = 300 s Optimum Temperature Range Q1 Control FET Q2 Sync FET Q1 Control FET Q2 Sync FET Value
60 V -4 V < VGS < 6 V 23 A 23 A 215 A 215 A -40 C < TJ < 150 C Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 1 EPC2102 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
STATIC CHARACTERISTICS Parameter
Maximum Drain Source Voltage (BVDSS) Maximum Drain Source Leakage Maximum RDS(on) Typical RDS(on) Gate Source Threshold Voltage Gate Source Maximum Positive Leakage Gate Source Maximum Negative Leakage
TJ = 25 C unless otherwise stated Conditions
Q1: VGS = 0 V, ID = 430 A Q2: VGS = 0 V, ID = 430 A VDS = 48 V, VGS = 0 V VGS = 5 V, ID = 20 A VGS = 5 V, ID = 20 A Q1: ID = 7 mA, VDS = VGS Q2: ID = 7 mA, VDS = VGS VGS = 5 V VGS = -4 V Q1 Control FET Q2 Sync FET
60 V 360 A 4.4 m 3.2 m 360 A 4.4 m 3.2 m 0.8 V < VGS(TH) < 2.5 V 7 mA -360 A 7 mA -360 A DYNAMIC CHARACTER...

  • Series: EPC2102 (1)
    • EPC2102ENG
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