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Datasheet Efficient Power Conversion EPC EPC2103ENG

Manufacturer:Efficient Power Conversion
Series:EPC2103
Part Number:EPC EPC2103ENG

­ 80 V Enhancement-Mode GaN Power Transistor Half Bridge

Datasheets

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    EPC2103 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
    Features: Greater than 97% System Efficiency at 20 A o o 48 VIN to 12 VOUT, 500 kHz Includes driver, inductor, and output filter High Frequency Operation High Density Footprint Low Inductance Package Pb-Free (RoHS Compliant), Halogen Free Applications: High Frequency DC-DC Conversion
    98.5 EPC2103 devices are supplied only in passivated die form with solder balls Die Size: 6.05 mm x 2.3 mm Typical System Efficiency Typical Circuit
    Efficiency (%) 98 97.5 97 96.5 96 95.5 95 94.5 94 0 2 4 6 8 10 12 14 16 18 20 22 24 26 fsw=300 kHz fsw=500 kHz Output Current (A) VIN = 48 V, VOUT = 12 V MAXIMUM RATINGS Parameter
    Maximum Drain Source Voltage (VSW to PGND, VIN to VSW) Maximum Gate Source Voltage Range (Gate 1 to VSW, Gate 2 to PGND) Continuous Drain Current, 25 C, RJA = 22 (Q1), 22 (Q2) Maximum Pulsed Drain Current, 25 C, Tpulse = 300 s Optimum Temperature Range Q1 Control FET Q2 Sync FET Q1 Control FET Q2 Sync FET Value
    80 V -4 V < VGS < 6 V 23 A 23 A 195 A 195 A -40 C < TJ < 150 C Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 1 EPC2103 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
    STATIC CHARACTERISTICS Parameter
    Maximum Drain Source Voltage (BVDSS) Maximum Drain Source Leakage Maximum RDS(on) Typical RDS(on) Gate Source Threshold Voltage Gate Source Maximum Positive Leakage Gate Source Maximum Negative Leakage
    TJ = 25 C unless otherwise stated Conditions
    Q1: VGS = 0 V, ID = 430 A Q2: VGS = 0 V, ID = 430 A VDS = 64 V, VGS = 0 V VGS = 5 V, ID = 20 A VGS = 5 V, ID = 20 A Q1: ID = 7 mA, VDS = VGS Q2: ID = 7 mA, VDS = VGS VGS = 5 V VGS = -4 V Q1 Control FET Q2 Sync FET
    80 V 325 A 5.5 m 3.8 m 325 A 5.5 m 3.8 m 0.8 V < VGS(TH) < 2.5 V 6.5 mA -325 A 6.5 mA -325 A DYNAMIC CHARACTERISTICS Parameter
    CISS (Input Capacitance) COSS (Output Capacitance) CRSS (Reverse Transfer Capacitance) QG (Total Gate Charge) QGS (Gate to Source Charge) QGD (Gate to Drain Charge) QG(TH) (Gate Charge at Threshold) QOSS (Output Charge) QRR (Source-Drain Recovery Charge)
    TJ = 25 C unless otherwise stated Conditions
    VDS = 40 V, VGS = 0 V
    VDS = 40 V, ID = 20 A, VGS = 5 V Typical Value Q1 Control FET Q2 Sync FET Unit
    0.76 0.46 0.0087 6.5 2 1.3 1.5 29 0 0.76 0.63 0.0087 6.5 2 1.3 1.5 39 0 nC nF VDS = 40 V, ID = 20 A VDS = 40 V, VGS = 0 V Subject to Change without Notice www.epc-co.com COPYRIGHT 2015 Page 2 EPC2103 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
    THERMAL CHARACTERISTICS ...

Prices

Docket:
EPC2103 Enhancement-Mode GaN Power Transistor Half Bridge Preliminary Specification Sheet
Features: Greater than 97% System Efficiency at 20 A o o 48 VIN to 12 VOUT, 500 kHz Includes driver, inductor, and output filter High Frequency Operation High Density Footprint Low Inductance Package Pb-Free (RoHS Compliant), Halogen Free Applications: High Frequency DC-DC Conversion
98.5 EPC2103 devices are supplied only in passivated die form with solder balls Die Size: 6.05 mm x 2.3 mm Typical System Efficiency Typical Circuit
Efficiency (%) 98 97.5 97 96.5 96 95.5 95 94.5 94 0 2 4 6 8 10 12 14 16 18 20 22 24 26 fsw=300 kHz fsw=500 kHz Output Current (A) VIN = 48 V, VOUT = 12 V MAXIMUM RATINGS Parameter
Maximum Drain Source Voltage (VSW to PGND, VIN to VSW) Maximum Gate Source Voltage Range (Gate 1 to VSW, Gate 2 to PGND) Continuous Drain Current, 25 C, RJA = 22 (Q1), 22 (Q2) Maximum Pulsed Drain Current, 25 C, Tpulse = 300 s Optimum Temperature Range Q1 Control FET Q2 Sync FET Q1 Control FET Q2 Sync FET Value
80 V -4 V < VGS < 6 V 23 A 23 A 195 A 195 A -40 C < TJ < 150 C Subj...

  • Series: EPC2103 (1)
    • EPC EPC2103ENG
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