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Datasheet Analog Devices AD9680BCPZ-1000

Analog Devices AD9680BCPZ-1000

Manufacturer:Analog Devices
Series:AD9680
Part Number:AD9680BCPZ-1000

14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

Documents:

Other Names: AD9680BCPZ1000, AD9680BCPZ 1000

Docket:
Data Sheet
FEATURES 14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter AD9680
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD (1.25V) (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.8V TO 3.3V) BUFFER DDC
JESD204B HIGH SPEED SERIALIZER JESD204B (Subclass 1) coded serial digital outputs 1.65 W total power per channel at 1 GSPS (default settings) SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = -1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = -1.0 dBFS) ENOB = 10.8 bits at 10 MHz DNL = 0.5 LSB INL = 2.5 LSB Noise density = -154 dBFS/Hz at 1 GSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation No missing codes Internal ADC voltage reference Flexible input range AD9680-1000 and AD9680-820: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal) AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) Programmable termination impedance 400 , 200 , 100 , and 50 differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 cascaded half-band filters Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither VIN+A VINA ADC CORE 14 Tx OUTPUTS FAST DETECT FD_A SIGNAL MONITOR 4 FD_B VIN+B VINB SERDOUT0 SERDOUT1 SERDOUT2 SERDOUT3 14 ADC CORE BUFFER DDC V_1P0 CONTROL REGISTERS FAST DETECT JESD204B SUBCLASS 1 CONTROL SYNCINB SYSREF CLOCK GENERATION CLK+ CLK SIGNAL MONITOR...

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