Datasheet Texas Instruments ADS6125

ManufacturerTexas Instruments
SeriesADS6125
Datasheet Texas Instruments ADS6125

12-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

Datasheets

12-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS and CMOS OUTPUTS datasheet
PDF, 2.4 Mb, Revision: A, File published: Dec 4, 2007
Extract from the document
Datasheet

Prices

Status

ADS6125IRHBRADS6125IRHBTADS6125IRHBTG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Packaging

ADS6125IRHBRADS6125IRHBTADS6125IRHBTG4
N123
Pin323232
Package TypeRHBRHBRHB
Industry STD TermVQFNVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-N
Package QTY3000250250
CarrierLARGE T&RSMALL T&RSMALL T&R
Device MarkingAZ6125AZ6125AZ6125
Width (mm)555
Length (mm)555
Thickness (mm).9.9.9
Pitch (mm).5.5.5
Max Height (mm)111
Mechanical DataDownloadDownloadDownload

Parametrics

Parameters / ModelsADS6125IRHBR
ADS6125IRHBR
ADS6125IRHBT
ADS6125IRHBT
ADS6125IRHBTG4
ADS6125IRHBTG4
# Input Channels111
Analog Input BW, MHz500500
Analog Input BW(MHz)500
Approx. Price (US$)27.01 | 1ku
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB22
DNL(Max)(+/-LSB)2
DNL(Typ), +/-LSB0.60.6
ENOB, Bits11.411.4
ENOB(Bits)11.4
INL(Max), +/-LSB22
INL(Max)(+/-LSB)2
INL(Typ), +/-LSB11
Input BufferNoNo
Input Range222V (p-p)
InterfaceDDR LVDS,Parallel CMOSDDR LVDS,Parallel CMOSParallel LVDS
Serial SPI Interface
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Package GroupVQFNVQFNVQFN
Package Size(mm2=WxL)32VQFN: 25 mm2: 5 x 5
Package Size: mm2:W x L, PKG32VQFN: 25 mm2: 5 x 5(VQFN)32VQFN: 25 mm2: 5 x 5(VQFN)
Power Consumption(Typ), mW417417
Power Consumption(Typ)(mW)417
RatingCatalogCatalogCatalog
Reference ModeExt,IntExt,IntExt
Int
Resolution, Bits1212
Resolution(Bits)12
SFDR, dB8080
SFDR(dB)80
SINAD, dB70.670.6
SINAD(dB)70.6
SNR, dB71.371.3
SNR(dB)71.3
Sample Rate (max)(SPS)125MSPS
Sample Rate(Max), MSPS125125

Eco Plan

ADS6125IRHBRADS6125IRHBTADS6125IRHBTG4
RoHSCompliantCompliantCompliant
Pb FreeYes

Application Notes

  • Band-Pass Filter Design Techniques for High-Speed ADCs
    PDF, 733 Kb, File published: Feb 27, 2012
    Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the
  • QFN Layout Guidelines
    PDF, 1.3 Mb, File published: Jul 28, 2006
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, File published: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, File published: May 18, 2015

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
EMS supplier