Datasheet Texas Instruments ADS805

ManufacturerTexas Instruments
SeriesADS805
Datasheet Texas Instruments ADS805

12-Bit, 20-MSPS Analog-to-Digital Converter (ADC)

Datasheets

12-Bit, 20MHz Sampling Analog-To-Digital Converter (Rev. B)
PDF, 862 Kb, Revision: B, File published: Jul 18, 2002
12-Bit, 20MHz Sampling Analog-To-Digital Converter datasheet
PDF, 812 Kb, Revision: B, File published: Jul 18, 2002
Extract from the document

Prices

Status

ADS805EADS805E/1KADS805EG4ADS805UADS805U/1K
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNoNoNoNoNo

Packaging

ADS805EADS805E/1KADS805EG4ADS805UADS805U/1K
N12345
Pin2828282828
Package TypeDBDBDBDWDW
Industry STD TermSSOPSSOPSSOPSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY50100050
CarrierTUBELARGE T&RTUBE
Device MarkingADS805EADS805EADS805E
Width (mm)5.35.35.37.57.5
Length (mm)10.210.210.217.917.9
Thickness (mm)1.951.951.952.352.35
Pitch (mm).65.65.651.271.27
Max Height (mm)2222.652.65
Mechanical DataDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsADS805E
ADS805E
ADS805E/1K
ADS805E/1K
ADS805EG4
ADS805EG4
ADS805U
ADS805U
ADS805U/1K
ADS805U/1K
# Input Channels11111
Analog Input BW, MHz270270
Analog Input BW(MHz)270270270
Approx. Price (US$)11.95 | 1ku11.95 | 1ku11.95 | 1ku
ArchitecturePipelinePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB0.750.75
DNL(Max)(+/-LSB)0.750.750.75
DNL(Typ), +/-LSB0.250.25
ENOB, Bits10.710.7
ENOB(Bits)0.250.250.25
INL(Max), +/-LSB22
INL(Max)(+/-LSB)111
INL(Typ), +/-LSB11
Input BufferNoNoNoNo
Input Range2,52,52V / 5V(p-p)2V / 5V(p-p)2V / 5V(p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85-40 to 85
Package GroupSSOPSSOPSSOPSSOPSSOP
Package Size(mm2=WxL)28SSOP: 80 mm2: 7.8 x 10.2
Package Size: mm2:W x L, PKG28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Package Size: mm2:W x L (PKG)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Power Consumption(Typ), mW300300
Power Consumption(Typ)(mW)300300300
RatingCatalogCatalogCatalogCatalogCatalog
Reference ModeExt,IntExt,IntInt
Ext
Ext
Int
Ext
Int
Resolution, Bits1212
Resolution(Bits)121212
SFDR, dB7474
SFDR(dB)747474
SINAD, dB6666
SINAD(dB)666666
SNR, dB6868
SNR(dB)686868
Sample Rate (max)(SPS)20MSPS
Sample Rate(Max), MSPS2020
Sample Rate(Max)(MSPS)2020

Eco Plan

ADS805EADS805E/1KADS805EG4ADS805UADS805U/1K
RoHSCompliantCompliantCompliantNot CompliantNot Compliant
Pb FreeYesNoNo

Application Notes

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, File published: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, File published: May 18, 2015
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, File published: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, File published: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
EMS supplier