Datasheet Texas Instruments THS1031

ManufacturerTexas Instruments
SeriesTHS1031
Datasheet Texas Instruments THS1031

10-Bit, 30-MSPS Analog-to-Digital Converter (ADC)

Datasheets

3-V to 5.5-V, 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter datasheet
PDF, 728 Kb, Revision: E, File published: Mar 21, 2002
Extract from the document
3-V to 5.5-V, 10-Bit, 30 MSPS CMOS Analog-to-Digital Converter (Rev. E)
PDF, 728 Kb, Revision: E, File published: Mar 21, 2002

Prices

Status

THS1031CDWTHS1031CPWTHS1031CPWRTHS1031CPWRG4THS1031IDWTHS1031IPWTHS1031IPWG4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNo

Packaging

THS1031CDWTHS1031CPWTHS1031CPWRTHS1031CPWRG4THS1031IDWTHS1031IPWTHS1031IPWG4
N1234567
Pin28282828282828
Package TypeDWPWPWPWDWPWPW
Industry STD TermSOICTSSOPTSSOPTSSOPSOICTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Device MarkingTH1031TH1031TH1031TH1031TJ1031TJ1031
Width (mm)7.54.44.44.47.54.44.4
Length (mm)17.99.79.79.717.99.79.7
Thickness (mm)2.351112.3511
Pitch (mm)1.27.65.65.651.27.65.65
Max Height (mm)2.651.21.21.22.651.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownload
Package QTY5020002000
CarrierTUBELARGE T&RLARGE T&R

Parametrics

Parameters / ModelsTHS1031CDW
THS1031CDW
THS1031CPW
THS1031CPW
THS1031CPWR
THS1031CPWR
THS1031CPWRG4
THS1031CPWRG4
THS1031IDW
THS1031IDW
THS1031IPW
THS1031IPW
THS1031IPWG4
THS1031IPWG4
# Input Channels1111111
Analog Input BW, MHz150150
Analog Input BW(MHz)150150150150150
Approx. Price (US$)7.67 | 100u7.67 | 100u7.67 | 100u7.67 | 100u7.67 | 100u
ArchitecturePipelinePipelinePipelinePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB11
DNL(Max)(+/-LSB)11111
DNL(Typ), +/-LSB0.30.3
ENOB, Bits8.88.8
ENOB(Bits)7.77.77.77.77.7
INL(Max), +/-LSB22
INL(Max)(+/-LSB)22222
INL(Typ), +/-LSB11
Input BufferNoNoNoNoNoNo
Input Range2V (p-p)222V (p-p)2V (p-p)2V (p-p)2V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C0 to 700 to 70
Operating Temperature Range(C)0 to 700 to 700 to 700 to 700 to 70
Package GroupTSSOPTSSOPTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size(mm2=WxL)28TSSOP: 62 mm2: 6.4 x 9.7
Package Size: mm2:W x L, PKG28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Package Size: mm2:W x L (PKG)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ), mW160160
Power Consumption(Typ)(mW)160160160160160
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExt
Int
Ext,IntExt,IntInt
Ext
Ext
Int
Ext
Int
Ext
Int
Resolution, Bits1010
Resolution(Bits)1010101010
SFDR, dB52.452.4
SFDR(dB)52.452.452.452.452.4
SINAD, dB5656
SINAD(dB)5656565656
SNR, dB49.349.3
SNR(dB)49.349.349.349.349.3
Sample Rate (max)(SPS)30MSPS
Sample Rate(Max), MSPS3030
Sample Rate(Max)(MSPS)30303030

Eco Plan

THS1031CDWTHS1031CPWTHS1031CPWRTHS1031CPWRG4THS1031IDWTHS1031IPWTHS1031IPWG4
RoHSNot CompliantCompliantCompliantCompliantNot CompliantNot CompliantNot Compliant
Pb FreeNoNoYesNoNo

Application Notes

  • Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPs
    PDF, 249 Kb, File published: Jun 8, 2001
    Most high-speed data converters cannot be connected directly to a digital signal processor (DSP). The required transfer rates would tie up most of the DSP's I/O bandwidth. A FIFO is an appropriate solution for this problem because it can buffer a large block of data, and the DSP can read data from the FIFO in a burst mode. This is much more efficient compared to single reads for every sampled valu
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, File published: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revision: A, File published: Jan 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
EMS supplier