Datasheet Texas Instruments TLC5510A

Manufacturer	Texas Instruments
Series	TLC5510A

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Parametrics

Parameters / Models	TLC5510AINS	TLC5510AINSLE	TLC5510AINSR
# Input Channels	1	1	1
Analog Input BW, MHz	14		14
Analog Input BW(MHz)		14
Approx. Price (US$)		2.59 | 1ku
Architecture	Flash	Flash	Flash
DNL(Max), +/-LSB	0.75		0.75
DNL(Max)(+/-LSB)		0.75
DNL(Typ), +/-LSB	0.3		0.3
ENOB, Bits	6.8		6.8
INL(Max), +/-LSB	1		1
INL(Max)(+/-LSB)		1
INL(Typ), +/-LSB	0.4		0.4
Input Buffer	No	No	No
Input Range, Vp-p	4	+2V	4
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C	-20 to 75		-20 to 75
Operating Temperature Range(C)		-20 to 75
Package Group	SO	SO	SO
Package Size: mm2:W x L, PKG	24SO: 117 mm2: 7.8 x 15(SO)		24SO: 117 mm2: 7.8 x 15(SO)
Package Size: mm2:W x L (PKG)		24SO: 117 mm2: 7.8 x 15(SO)
Power Consumption(Typ), mW	150		150
Power Consumption(Typ)(mW)		150
Rating	Catalog	Catalog	Catalog
Reference Mode	Ext	Ext	Ext
Resolution, Bits	8		8
Resolution(Bits)		8
SFDR, dB	42		42
SFDR(dB)		42
SINAD, dB	44		44
SNR, dB	46		46
SNR(dB)		46
Sample Rate(Max), MSPS	20		20
Sample Rate(Max)(MSPS)		20

Eco Plan

Application Notes

• Download
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, File published: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Download
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, File published: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Download
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

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Manufacturer's Classification

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)