Datasheet Texas Instruments TMS320C6413ZTS500
| Manufacturer | Texas Instruments |
| Series | TMS320C6413 |
| Part Number | TMS320C6413ZTS500 |
Fixed-Point Digital Signal Processor 288-FCBGA
Datasheets
TMS320C6413, TMS320C6410 Fixed-Point Digital Signal Processors datasheet
PDF, 1.8 Mb, Revision: F, File published: Jan 16, 2006
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 288 | 288 | 288 |
| Package Type | ZTS | ZTS | ZTS |
| Industry STD Term | FCBGA | FCBGA | FCBGA |
| JEDEC Code | S-PBGA-N | S-PBGA-N | S-PBGA-N |
| Package QTY | 60 | 60 | 60 |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
| Device Marking | ZTS500 | TMS | 320C6413 |
| Width (mm) | 23 | 23 | 23 |
| Length (mm) | 23 | 23 | 23 |
| Thickness (mm) | 1.9 | 1.9 | 1.9 |
| Pitch (mm) | 1 | 1 | 1 |
| Max Height (mm) | 2.8 | 2.8 | 2.8 |
| Mechanical Data | Download | Download | Download |
Eco Plan
| RoHS | Compliant |
| Pb Free | Yes |
Design Kits & Evaluation Modules
- JTAG Emulators/ Analyzers: TMDSEMU560V2STM-U
XDS560v2 System Trace USB Debug Probe
Lifecycle Status: Active (Recommended for new designs) - JTAG Emulators/ Analyzers: XDS560TRACE
XDS560 Trace Emulator
Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device) - JTAG Emulators/ Analyzers: TMDSEMU560V2STM-UE
XDS560v2 System Trace USB & Ethernet Debug Probe
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- TMS320C6413 Hardware Designer's Resource Guide (Rev. D)PDF, 149 Kb, Revision: D, File published: Oct 24, 2005
The TMS320C6413 DSP Hardware DesignerВ’s Resource Guide is a collection of the most commonly used technical documentation, and models for DSP hardware system designers. Topics covered include Getting Started, Models and Symbols, Bootloading, and Checklists to aid in your initial design and debug efforts. Each section includes pointers to valuable information including technical documentation, model - TMS320C6410/13 Power Consumption SummaryPDF, 64 Kb, File published: Sep 20, 2004
This document discusses the power consumption of the Texas Instruments TMS320C6410в„ў and TMS320C6413в„ў digital signal processors (DSPs). Power consumption on C64x devices is highly application-dependent, so a spreadsheet is provided to model power consumption for a user?s application. To get good results from the spreadsheet, realistic usage parameters must be entered. The low-core volta - TMS320C6000 Multichannel Communications System InterfacePDF, 107 Kb, File published: Feb 3, 2000
This document describes a simple interface for development of multichannel telephony systems. Three interfaces are provided: 1. MVIP (Multi-Vendor Integration Protocol): Accomplished with the MT90810, Flexible MVIP Interface Circuit (FMIC). 2. T1/E1 interface: Accomplished with the PEB2254, Framing and Line Interface Component (FALC).3. Voice Band Analog Input and Output: Accomplished - TMS320C6000 HPI Boot OperationPDF, 98 Kb, File published: Jan 6, 1999
The Texas Instruments (TI)(tm) TMS320C62x and TMS320C67x digital signal processors (DSPs) provide a variety of boot configurations that determine which actions the DSP should perform to prepare for initialization after device reset. The boot process is determined by latching the boot configuration settings at reset.The various boot processes load code from an external ROM memory space and from - TMS320C6000 EMIF to TMS320C6000 Host Port Interface (Rev. B)PDF, 372 Kb, Revision: B, File published: Sep 12, 2003
This application report describes the interface between the host port interface (HPI) and the external memory interface (EMIF) of the TMS320C6000в„ў digital signal processor (DSP). This report examines three possible pairings of the various TMS320C6000 devices: TMS320C6201/C6701 EMIF to TMS320C6201/C6701 HPI, TMS320C6211C/C6711 EMIF to TMS320C6211/C6711 HPI, and TMS320C64xв„ў EMIF to TMS3 - TMS320C64x Reference DesignPDF, 90 Kb, File published: May 12, 2004
TI provides a reference design with commonly used configurations that allow customers to get maximum performance effortlessly from TMS320C64xв„ў DSP based systems. For extreme high performance, an SDRAM only interface is designed to run at speeds up to 150 MHz. The reference design also includes a USB bridge and other common DSP attach circuitry. The designs are suitable for simple modular dro - TMS320C64x EDMA ArchitecturePDF, 250 Kb, File published: Mar 3, 2004
The enhanced DMA (EDMA) controller of the TMS320C64xв„ў device is a highly efficient data transfer engine. To maximize bandwidth, minimize transfer interference, and fully utilize the resources of the EDMA, it is crucial to understand the architecture of the engine. Transfer requests (TRs) originate from many requestors, including sixty-four programmable EDMA channels, the level 2 (L2) memory - TMS320C64x EDMA Performance DataPDF, 246 Kb, File published: Mar 5, 2004
The enhanced DMA (EDMA) controller of the TMS320C64xв„ў device is a highly efficient data transfer engine, capable of maintaining transfers at up to 2.4 GB/sec at a 600 MHz CPU clock frequency. This document details measured bandwidth achieved under various operating conditions. For more information on ideal transfer bandwidth and scheduling transfers, please consult TMS320C64x EDMA Architectu - Cache Usage in High-Performance DSP Applications with the TMS320C64xPDF, 129 Kb, File published: Dec 13, 2001
The TMS320C64xв„ў, the newest member of the TMS320C6000в„ў (C6000в„ў) family, is used in high-performance DSP applications. The C64xв„ў processes information at a rate of 4800 MIPs, while operating at a clock rate of 600 MHz. Processing data at these extremely high rates requires fast memory that is directly connected to the CPU (Central Processing Unit). However, a bandwidth dilem - TMS320C64x DSP Host Port Interface (HPI) PerformancePDF, 206 Kb, File published: Oct 24, 2003
This application report describes the number of CPU cycles required to perform a given host port interface (HPI) data transfer based on a variety of permutations of burst length, CPU speed, EMIF speed, etc.The HPI provides direct connectivity between a host processor and a CPU?s memory space via a 32/16-bit parallel port. The HPI throughput between a host processor and the TMS320C64xв„ў DSP - TMS320C6000 Enhanced DMA: Example Applications (Rev. A)PDF, 1.4 Mb, Revision: A, File published: Oct 24, 2001
The enhanced direct memory access (EDMA) controller is the backbone of the two-level cache architecture for the TMS320C6000? DSPs. The EDMA performs:o cache servicingo host-port servicingo user-programmable data transfers Through proper configuration, EDMA channels can be set up to operate continuously without requiring CPU intervention or reprogramming. This allows the CPU to use its - Use and Handling of Semiconductor Packages With ENIG Pad FinishesPDF, 129 Kb, File published: Aug 31, 2004
- TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A)PDF, 272 Kb, Revision: A, File published: Aug 31, 2001
This application report describes the interface between the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) host port and the Intel 80960 microprocessor. The document includes schematics showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing diagrams). - TMS320C6000 Host Port to MC68360 Interface (Rev. A)PDF, 261 Kb, Revision: A, File published: Sep 30, 2001
This application report describes an interface between the Motorola MC68360 quad integrated communication controller (QUICC) and the host port interface (HPI) of a TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This includes a schematic showing connections between the two devices and verification that timing requirements are met for each device (tables and timing diagrams - TMS320C6000 Host Port to MPC860 Interface (Rev. A)PDF, 311 Kb, Revision: A, File published: Jun 21, 2001
This application report describes an interface between the Motorola MPC860 microprocessor and the host port interface (HPI) of a Texas Instruments TMS320C6000в„ў (C6000в„ў) digital signal processor (DSP) device. This document includes a schematic showing connections between the two devices, PAL equations, and verification that timing requirements are met for each device (tables and timing - General Guide to Implement Logarithmic and Exponential Operations on Fixed-PointPDF, 50 Kb, File published: Jan 31, 2000
Modern audio and video compression algorithms usually take the advantage of logarithmic characteristics of human ears and eyes. This approach greatly reduces the redundancy in signals being processed. However, it poses a requirement on fixed-point DSPs to handle these logarithmic and exponential operations.This application report provides a general guide to implement these operations on fixed- - TMS320C6000 McBSP as a TDM Highway (Rev. A)PDF, 313 Kb, Revision: A, File published: Sep 11, 2000
This document describes how the multichannel buffered serial ports (McBSP) in the TMS320C6000в„ў digital signal processors (DSP) are used to communicate on a time-division multiplexed (TDM) data highway.TDM provides multiple devices a time slot to perform data transfer. Thus, multiple users operate various channels; however, each user has a set of channel(s) assigned for transmission and re - TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B)PDF, 87 Kb, Revision: B, File published: Jun 4, 2002
This document describes how the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) are used to communicate to a single-rate Serial Telecom (ST)-BUS-compliant device.The McBSP receives the framing signal, clock, and data from the ST-BUSв„ў device and processes them to generate internal frame syncs and clocks for correct data - TMS320C6000 Board Design for JTAG (Rev. C)PDF, 89 Kb, Revision: C, File published: Apr 2, 2002
Designing a TMS320C6000в„ў DSP board to utilize all of the functionality of the JTAG scan path is a simple process, but a few considerations must be taken into account. The default state of the emulation signals determines whether the JTAG port is used for emulation or for boundary scan. It is therefore necessary to provide flexibility in the design to accommodate those modes that are desired. - TMS320C6000 McBSP Initialization (Rev. C)PDF, 232 Kb, Revision: C, File published: Mar 8, 2004
The TMS320C6000? multichannel buffered serial port (McBSP) can operate in a variety of modes, as per application requirements. For proper operation, the serial port must be initialized in a specific order. This document describes the initialization steps necessary when either the (E)DMA or the CPU is used to service the McBSP data. Typically, the (E)DMA is used to perform read/write transfers from - Using a TMS320C6000 McBSP for Data Packing (Rev. A)PDF, 257 Kb, Revision: A, File published: Oct 31, 2001
This application report describes how to use the multichannel buffered serial port (McBSP) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) for data packing. Data packing involves moving either multiple successive 8-bit elements to/from the McBSP as a single 16/24/32-bit element or multiple successive 16-bit words to/from the McBSP as a single 32-bit word.The McBSP - Circular Buffering on TMS320C6000 (Rev. A)PDF, 172 Kb, Revision: A, File published: Sep 12, 2000
This application report explains how circular buffering is implemented on the TMS320C6000? devices. Circular buffering helps to implement finite impulse response (FIR) filters efficiently. Filters require delay lines or buffers of past (and current) samples. Circular addressing simplifies the manipulation of pointers in accessing the data samples.This application report addresses the following - TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A)PDF, 289 Kb, Revision: A, File published: Jul 10, 2001
This document describes how to use the multichannel buffered serial ports (McBSPs) in the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) as a digital controller for an audio codec 1997 device.The McBSP is connected to a stereo audio codec 1997 device. This application report uses the TLV320AIC27 audio codec (AIC27) as an example. The audio codec 1997 (AC'97) standard spec - TMS320C6000 u-Law and a-Law Companding with Software or the McBSPPDF, 150 Kb, File published: Feb 2, 2000
This document describes how to perform data companding with the TMS320C6000(tm)digital signal processors(DSP). Companding refers to the compression and expansion of transfer data before and after transmission, respectively.The multichannel buffered serial port (McBSP) in the TMS320C6000 supports two companding formats: mu-Law and A-Law. Both companding formats are specified in the CCITT G.711 - TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A)PDF, 240 Kb, Revision: A, File published: Jul 23, 2001
This document describes how to interface the multichannel buffered serial port (McBSP) in the TMS320C6000? digital signal processor (DSP) to a voice band audio processor (VBAP). The VBAP under discussion is the TI TLV320AC56, 3V, 2.048 MHz audio processor which is a m-law companding device. The interface is also applicable to TI?s TLV320AC57, an A-law companding audio processor.The highly - TMS320C6000 EMIF to External Flash Memory (Rev. A)PDF, 471 Kb, Revision: A, File published: Feb 13, 2002
Interfacing external flash memory to the Texas Instruments TMS320C6000в„ў digital signal processor (DSP) is simple compared to previous generations of TI DSPs. The TMS320C6000 advanced external memory interface (EMIF) provides a glueless interface to a variety of external memory devices.This document describes the following:EMIF control registers and asynchronous interface signals< - TMS320C6000 C Compiler: C Implementation of IntrinsicsPDF, 154 Kb, File published: Dec 7, 1999
The first optimization step that you can perform on C source code for the TMS320C62xx is to use intrinsic operators. Intrinsics are used like functions and produce assembly language statements that would otherwise be inexpressible in C. The problem is that once you have performed the first optimization step, your C source code is no longer ANSI C compatible. The code proposed within this appli - TMS320C6000 McBSP: IOM-2 Interface (Rev. A)PDF, 284 Kb, Revision: A, File published: May 21, 2001
This document describes how the multi-channel buffered serial port (McBSP) in the Texas Instruments (TI) TMS320C6000? (C6000?) digital signal processor (DSP) family is used to communicate to an ISDN Oriented Modular Interface Revision 2 (IOM-2) bus-compliant device. This document also describes the usage of McBSP registers and sample code to perform the above function. - TMS320C6000 Board Design: Considerations for Debug (Rev. C)PDF, 96 Kb, Revision: C, File published: Apr 21, 2004
- TMS320C6000 McBSP: Interface to SPI ROM (Rev. C)PDF, 99 Kb, Revision: C, File published: Jun 30, 2001
The TMS320C6000? (C6000?) Multichannel Buffered Serial Port (McBSP) is designed to interface to a device that supports synchronous Serial Peripheral Interface (SPI). This document describes the hardware interface between the McBSP and a SPI ROM. The McBSP operates as the master in a user-specified clock stop (CLKSTP) mode in order to communicate with the SPI ROM. The McBSP initialization and contr - TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E)PDF, 833 Kb, Revision: E, File published: Sep 4, 2007
Interfacing external SDRAM to the Texas Instruments TMS320C6000™ digital signal processor (DSP) is simple, compared to previous generations of TI DSPs, because of the advanced external memory interface (EMIF). The EMIF is a glueless interface to a variety of external memory devices.This application report describes the EMIF’s control registers and SDRAM signals along with SDRAM function - TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D)PDF, 185 Kb, Revision: D, File published: Apr 26, 2004
Texas Instruments TMS320C6000в„ў digital signal processors (DSPs) provide a variety of boot configurations that determine which actions are performed after device reset, to prepare for initialization. The boot process is determined by latching the boot configuration settings at reset.The boot process performed by the DSP is to either load code from an external read-only memory (ROM) space - TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A)PDF, 118 Kb, Revision: A, File published: Aug 31, 2001
Interfacing external asynchronous static RAM (ASRAM) to the Texas Instruments (TIв„ў) TMS320C6000 series of digital signal processors (DSPs) is simple compared to previous generations of TI DSPs, thanks to the advanced external memory interface (EMIF). The EMIF provides a glueless interface to a variety of external memory devices.This document describes:EMIF control registers and ASR - Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A)PDF, 296 Kb, Revision: A, File published: Aug 31, 2001
This document describes how to use the mulit-channel buffered serial ports (McBSP) in the Texas Instruments (TI) TMS320C6000в„ў digital signal processor (DSP) as a high-speed data communication port.One McBSP of one C6000в„ў DSP device can be connected to a McBSP on another C6000 DSP device to serve as a high-speed data communication port. Typically, McBSPs of similar device numbers a - Using IBIS Models for Timing Analysis (Rev. A)PDF, 301 Kb, Revision: A, File published: Apr 15, 2003
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d - TMS320C6000 EDMA IO Scheduling and PerformancePDF, 269 Kb, File published: Mar 5, 2004
The enhanced DMA (EDMA) is a highly efficient and parallel data transfer engine. To make the best use of its resources, it is necessary to understand the architecture and schedule transfers intelligently. This document details how to summarize, analyze, and schedule system traffic to produce efficient designs. An example audio/video system is presented and analyzed in full. Finally, EDMA performan - TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)PDF, 310 Kb, Revision: A, File published: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP - Thermal Considerations for the DM64xx, DM64x, and C6000 DevicesPDF, 127 Kb, File published: May 20, 2007
As integrated circuit (IC) components become more complex, the challenge of producing an end product with superior thermal performance increases. Thermal performance is a system level concern, impacted by IC packaging as well as by printed circuit board (PCB) design. This application report addresses the thermal considerations for the TMS320DM64xx, TMS320DM64x, and TMS320C6000в„ў DSP devices. - Common Object File Format (COFF)PDF, 125 Kb, File published: Apr 15, 2009
- Introduction to TMS320C6000 DSP OptimizationPDF, 535 Kb, File published: Oct 6, 2011
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then
Model Line
Series: TMS320C6413 (4)
- TMS320C6413GTS500 TMS320C6413GTSA500 TMS320C6413ZTS500 TMS320C6413ZTSA500
Manufacturer's Classification
- Semiconductors > Processors > Digital Signal Processors > C6000 DSP > Other C6000 DSP
