Datasheet Texas Instruments ADS8481RGZR
| Manufacturer | Texas Instruments |
| Series | ADS8481 |
| Part Number | ADS8481RGZR |
18 Bit 1MSPS parallel ADC W/Ref 48-VQFN -40 to 85
Datasheets
18-Bit 1-MSPS Pseudo-Diff Unipolar Input Micro Samp ADC w/Parallell Interface datasheet
PDF, 1.3 Mb, Revision: A, File published: Mar 27, 2006
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Prices
Status
| Lifecycle Status | Preview (Device has been announced but is not in production. Samples may or may not be available) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 48 |
| Package Type | RGZ |
| Industry STD Term | VQFN |
| JEDEC Code | S-PQFP-N |
| Width (mm) | 7 |
| Length (mm) | 7 |
| Thickness (mm) | .9 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 1 |
| Analog Voltage AVDD(Max)(V) | 5.25 |
| Analog Voltage AVDD(Min)(V) | 4.75 |
| Approx. Price (US$) | 16.70 | 1ku |
| Architecture | SAR |
| Digital Supply(Max)(V) | 5.25 |
| Digital Supply(Min)(V) | 2.7 |
| INL(Max)(+/-LSB) | 3.5 |
| Input Range(Max)(V) | 4.1 |
| Input Type | Pseudo-Differential Single-Ended |
| Integrated Features | Oscillator |
| Interface | Parallel |
| Multi-Channel Configuration | N/A |
| Operating Temperature Range(C) | -40 to 85 |
| Package Group | VQFN |
| Package Size: mm2:W x L (PKG) | 48VQFN: 49 mm2: 7 x 7(VQFN) |
| Power Consumption(Typ)(mW) | 220 |
| Rating | Catalog |
| Reference Mode | Ext Int |
| Resolution(Bits) | 18 |
| SINAD(dB) | 93 |
| SNR(dB) | 94 |
| Sample Rate (max)(SPS) | 1MSPS |
| THD(Typ)(dB) | -112 |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: ADS8481EVM
ADS8481EVM Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
Model Line
Series: ADS8481 (4)
- ADS8481IBRGZT ADS8481IBRGZTG4 ADS8481IRGZT ADS8481RGZR
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)
