Datasheet Texas Instruments 66AK2H14

Manufacturer	Texas Instruments
Series	66AK2H14

Multicore DSP+ARM KeyStone II System-on-Chip (SoC)

Datasheets

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PDF, 2.4 Mb, Revision: F, File published: Jun 2, 2017

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Status

	66AK2H14BAAW24	66AK2H14BAAWA24	66AK2H14BXAAW24	66AK2H14DAAW24	66AK2H14DAAWA24	66AK2H14DXAAWA24
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	Yes	No	No	No

Packaging

	66AK2H14BAAW24	66AK2H14BAAWA24	66AK2H14BXAAW24	66AK2H14DAAW24	66AK2H14DAAWA24	66AK2H14DXAAWA24
N	1	2	3	4	5	6
Pin	1517	1517	1517	1517	1517	1517
Package Type	AAW	AAW	AAW	AAW	AAW	AAW
Package QTY	21	21	21	21	21	1
Carrier	JEDEC TRAY (5+1)	JEDEC TRAY (5+1)		JEDEC TRAY (5+1)	JEDEC TRAY (5+1)	JEDEC TRAY (5+1)
Device Marking	66AK2H14AAW	A1.2GHZ/1.4GHZ	1.2GHZ/1.4GHZ	1.2GHZ/1.4GHZ	A1.2GHZ/1.4GHZ	@2012 TI
Width (mm)	40	40	40	40	40	40
Length (mm)	40	40	40	40	40	40
Thickness (mm)	3.07	3.07	3.07	3.07	3.07	3.07
Mechanical Data	Download	Download	Download	Download	Download	Download

Parametrics

Parameters / Models	66AK2H14BAAW24	66AK2H14BAAWA24	66AK2H14BXAAW24	66AK2H14DAAW24	66AK2H14DAAWA24	66AK2H14DXAAWA24
ARM CPU	4 ARM Cortex-A15	4 ARM Cortex-A15	4 ARM Cortex-A15	4 ARM Cortex-A15	4 ARM Cortex-A15	4 ARM Cortex-A15
ARM MHz, Max.	1200,1400	1200,1400	1200,1400	1200,1400	1200,1400	1200,1400
Applications	Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space	Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space	Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space	Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space	Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space	Automation and Process,Avionics and Defense,Communications and Telecom,Consumer Electronics,Industrial,Medical,Security,Space
DRAM	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L	DDR3,DDR3L
DSP	8 C66x	8 C66x	8 C66x	8 C66x	8 C66x	8 C66x
DSP MHz, Max.	1200	1200	1200	1200	1200	1200
EMAC	10G Ethernet	10G Ethernet	10G Ethernet	10G Ethernet	10G Ethernet	10G Ethernet
Hardware Accelerators	Packet Accelerator,Security Accelerator	Packet Accelerator,Security Accelerator	Packet Accelerator,Security Accelerator	Packet Accelerator,Security Accelerator	Packet Accelerator,Security Accelerator	Packet Accelerator,Security Accelerator
I2C	3	3	3	3	3	3
On-Chip L2 Cache	4096 KB (ARM Cluster),1024 KB (per C66x DSP core)	4096 KB (ARM Cluster),1024 KB (per C66x DSP core)	4096 KB (ARM Cluster),1024 KB (per C66x DSP core)	4096 KB (ARM Cluster),1024 KB (per C66x DSP core)	4096 KB (ARM Cluster),1024 KB (per C66x DSP core)	4096 KB (ARM Cluster),1024 KB (per C66x DSP core)
Operating Systems	Integrity,Linux,SYS/BIOS,VxWorks	Integrity,Linux,SYS/BIOS,VxWorks	Integrity,Linux,SYS/BIOS,VxWorks	Integrity,Linux,SYS/BIOS,VxWorks	Integrity,Linux,SYS/BIOS,VxWorks	Integrity,Linux,SYS/BIOS,VxWorks
Operating Temperature Range, C	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85	-40 to 100,0 to 85
Other On-Chip Memory	6144 KB	6144 KB	6144 KB	6144 KB	6144 KB	6144 KB
PCI/PCIe	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2	2 PCIe Gen2
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
SPI	3	3	3	3	3	3
UART, SCI	2	2	2	2	2	2
USB	1	1	1	1	1	1

Eco Plan

	66AK2H14BAAW24	66AK2H14BAAWA24	66AK2H14BXAAW24	66AK2H14DAAW24	66AK2H14DAAWA24	66AK2H14DXAAWA24
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

Application Notes

Download
PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)
PDF, 57 Kb, Revision: A, File published: May 19, 2017
Download
Keystone II DDR3 Initialization
PDF, 73 Kb, File published: Jan 26, 2015
This application report provides a step-to-step initialization guide for the Keystone II device DDR3 SDRAM controller.
Download
Throughput Performance Guide for KeyStone II Devices (Rev. B)
PDF, 866 Kb, Revision: B, File published: Dec 22, 2015
This application report analyzes various performance measurements of the KeyStone II family of processors. It provides a throughput analysis of the various support peripherals to different end-points and memory access.
Download
Keystone II DDR3 Debug Guide
PDF, 143 Kb, File published: Oct 16, 2015
This guide provides tools for use when debugging a failing DDR3 interface on a KeyStone II device.
Download
Power Management of KS2 Device (Rev. C)
PDF, 61 Kb, Revision: C, File published: Jul 15, 2016
This application report lists the steps to enable Class 0 Temperature Compensation (Class 0 TC) mode of SmartReflexв„ў Subsystem (SRSS) module available on such devices.
Download
Hardware Design Guide for KeyStone II Devices
PDF, 1.8 Mb, File published: Mar 24, 2014
Download
SERDES Link Commissioning on KeyStone I and II Devices
PDF, 138 Kb, File published: Apr 13, 2016
The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
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PCIe Use Cases for KeyStone Devices
PDF, 320 Kb, File published: Dec 13, 2011
Download
The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: вЂњint gvar;вЂќ gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
Download
Clocking Design Guide for KeyStone Devices
PDF, 1.5 Mb, File published: Nov 9, 2010
Download
Optimizing Loops on the C66x DSP
PDF, 585 Kb, File published: Nov 9, 2010
Download
DDR3 Design Requirements for KeyStone Devices (Rev. B)
PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
Download
Multicore Programming Guide (Rev. B)
PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
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TI DSP Benchmarking
PDF, 62 Kb, File published: Jan 13, 2016
This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
Download
Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as вЂњprocessorsвЂќ, вЂњSystem-on-chipвЂќ, or вЂњSoCвЂќ). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require

Model Line

Series: 66AK2H14 (6)

66AK2H14BAAW24 66AK2H14BAAWA24 66AK2H14BXAAW24 66AK2H14DAAW24 66AK2H14DAAWA24 66AK2H14DXAAWA24

Manufacturer's Classification

Semiconductors> Processors> Digital Signal Processors> C6000 DSP + ARM Processors> 66AK2x