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Datasheet Texas Instruments ADS5562

Datasheet Texas Instruments ADS5562

ManufacturerTexas Instruments

16-Bit, 80-MSPS Analog-to-Digital Converter (ADC)


  • Download » Datasheet PDF, 1.7 Mb, Revision: B, File published: Jan 13, 2016
    ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs datasheet
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    Design ADS5560, ADS5562
    SLWS207B – MAY 2008 – REVISED JANUARY 2016 ADS556x 16-Bit, 40 and 80 MSPS ADCs With DDR LVDS and CMOS Outputs The device is specified over the
    temperature range of –40°C to 85°C.
    Device Information(1)
    ADS5560 Medical Imaging, MRI
    Wireless Communications Infrastructure
    Software Defined Radio
    Test and Measurement Instrumentation
    High Definition Video PACKAGE BODY SIZE (NOM) VQFN (48) ADS5562 7.00 mm Г— 7.00 mm (1) For all available packages, see the orderable addendum at
    the end of the data sheet. Block Diagram 2 Applications industrial CLKP CLKOUTP CLOCKGEN CLKM DRGND The device can be put in an external reference mode,
    where the VCM pin behaves as the external
    reference input. For applications where power is
    important, the ADS556x device offers power down
    modes and automatic power scaling at lower sample
    rates. DRVDD 16-Bit Resolution
    Maximum Sample Rate: ...


Family: ADS5560, ADS5562


Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo


Package TypeRGZRGZ
Package QTY2500250
Device MarkingAZ5562AZ5562
Width (mm)77
Length (mm)77
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical DataDownload »Download »


# Input Channels11
Analog Input BW, MHz250250
DNL(Max), +/-LSB0.950.95
DNL(Typ), +/-LSB0.50.5
ENOB, Bits13.113.1
INL(Max), +/-LSB8.58.5
INL(Typ), +/-LSB33
Input BufferNoNo
Input Range, Vp-p3.63.6
InterfaceParallel CMOS,Parallel LVDSParallel CMOS,Parallel LVDS
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupVQFNVQFN
Package Size: mm2:W x L, PKG48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)
Power Consumption(Typ), mW865865
Reference ModeExt,IntExt,Int
Resolution, Bits1616
SFDR, dB8585
SINAD, dB80.580.5
SNR, dB8484
Sample Rate(Max), MSPS8080

Eco Plan


Application Notes

  • Download » Application Notes PDF, 1.3 Mb, File published: Jul 28, 2006
    QFN Layout Guidelines
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • Download » Application Notes PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
    Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  • Download » Application Notes PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
    Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  • Download » Application Notes PDF, 376 Kb, File published: Apr 28, 2009
    Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Download » Application Notes PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Download » Application Notes PDF, 2.3 Mb, File published: Jun 2, 2008
    Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Download » Application Notes PDF, 424 Kb, File published: Jun 8, 2008
    CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Download » Application Notes PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
    Principles of Data Acquisition and Conversion (Rev. A)
  • Download » Application Notes PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Download » Application Notes PDF, 69 Kb, Revision: A, File published: May 18, 2015
    Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)

Moldel Line

Series: ADS5562 (2)

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)

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