Datasheet Texas Instruments ADS820

ManufacturerTexas Instruments
SeriesADS820
Datasheet Texas Instruments ADS820

10-Bit, 20-MSPS Analog-to-Digital Converter (ADC)

Datasheets

10-Bit, 20MHz Sampling Analog-To-Digital Converter datasheet
PDF, 378 Kb, Revision: B, File published: Feb 14, 2005
Extract from the document
10-Bit, 20MHz Sampling Analog-To-Digital Converter (Rev. B)
PDF, 404 Kb, Revision: B, File published: Feb 14, 2005

Prices

Status

ADS820EADS820E/1KADS820UADS820UG4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNo

Packaging

ADS820EADS820E/1KADS820UADS820UG4
N1234
Pin28282828
Package TypeDBDBDWDW
Industry STD TermSSOPSSOPSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.5
Length (mm)10.210.217.917.9
Thickness (mm)1.951.952.352.35
Pitch (mm).65.651.271.27
Max Height (mm)222.652.65
Mechanical DataDownloadDownloadDownloadDownload
Package QTY2020
CarrierTUBETUBE
Device MarkingADS820UADS820U

Parametrics

Parameters / ModelsADS820E
ADS820E
ADS820E/1K
ADS820E/1K
ADS820U
ADS820U
ADS820UG4
ADS820UG4
# Input Channels1111
Analog Input BW, MHz65
Analog Input BW(MHz)656565
Approx. Price (US$)10.15 | 1ku10.15 | 1ku10.15 | 1ku
ArchitecturePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB1
DNL(Max)(+/-LSB)111
DNL(Typ), +/-LSB0.15
ENOB, Bits9.5
ENOB(Bits)9.59.59.5
INL(Max), +/-LSB2
INL(Max)(+/-LSB)222
INL(Typ), +/-LSB0.5
Input BufferNoNoNo
Input Range2V (p-p)2V (p-p)22V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85-40 to 85
Package GroupSOICSOICSOICSOIC
Package Size(mm2=WxL)28SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Package Size: mm2:W x L (PKG)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Power Consumption(Typ), mW200
Power Consumption(Typ)(mW)200200200
RatingCatalogCatalogCatalogCatalog
Reference ModeExt
Int
Ext
Int
Ext,IntInt
Ext
Resolution, Bits10
Resolution(Bits)101010
SFDR, dB62
SFDR(dB)626262
SINAD, dB60
SINAD(dB)606060
SNR, dB60
SNR(dB)606060
Sample Rate (max)(SPS)20MSPS
Sample Rate(Max), MSPS20
Sample Rate(Max)(MSPS)2020

Eco Plan

ADS820EADS820E/1KADS820UADS820UG4
RoHSNot CompliantNot CompliantCompliantCompliant
Pb FreeYesNoNo

Application Notes

  • ADS82x ADC with non-uniform sampling clock
    PDF, 234 Kb, File published: Feb 28, 2005
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, File published: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, File published: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, File published: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, File published: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
EMS supplier