Datasheet Texas Instruments CD4077B

ManufacturerTexas Instruments
SeriesCD4077B
Datasheet Texas Instruments CD4077B

CMOS Quad Exclusive-NOR Gate

Datasheets

CD4070B, CD4077B datasheet
PDF, 1.6 Mb, Revision: E, File published: Aug 21, 2003
Extract from the document

Prices

Status

CD4077BECD4077BEE4CD4077BMCD4077BM96CD4077BM96E4CD4077BM96G4CD4077BME4CD4077BMTCD4077BNSRCD4077BNSRG4CD4077BPW
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNoNo

Packaging

CD4077BECD4077BEE4CD4077BMCD4077BM96CD4077BM96E4CD4077BM96G4CD4077BME4CD4077BMTCD4077BNSRCD4077BNSRG4CD4077BPW
N1234567891011
Pin1414141414141414141414
Package TypeNNDDDDDDNSNSPW
Industry STD TermPDIPPDIPSOICSOICSOICSOICSOICSOICSOPSOPTSSOP
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY252550250025002500502502000200090
CarrierTUBETUBETUBELARGE T&RLARGE T&RLARGE T&RTUBESMALL T&RLARGE T&RLARGE T&RTUBE
Device MarkingCD4077BECD4077BECD4077BMCD4077BMCD4077BMCD4077BMCD4077BMCD4077BMCD4077BCD4077BCM077B
Width (mm)6.356.353.913.913.913.913.913.915.35.34.4
Length (mm)19.319.38.658.658.658.658.658.6510.310.35
Thickness (mm)3.93.91.581.581.581.581.581.581.951.951
Pitch (mm)2.542.541.271.271.271.271.271.271.271.270.65
Max Height (mm)5.085.081.751.751.751.751.751.75221.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsCD4077BE
CD4077BE
CD4077BEE4
CD4077BEE4
CD4077BM
CD4077BM
CD4077BM96
CD4077BM96
CD4077BM96E4
CD4077BM96E4
CD4077BM96G4
CD4077BM96G4
CD4077BME4
CD4077BME4
CD4077BMT
CD4077BMT
CD4077BNSR
CD4077BNSR
CD4077BNSRG4
CD4077BNSRG4
CD4077BPW
CD4077BPW
Bits44444444444
F @ Nom Voltage(Max), Mhz99999999999
ICC @ Nom Voltage(Max), mA0.0150.0150.0150.0150.0150.0150.0150.0150.0150.0150.015
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive, mA-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8-6.8/6.8
Package GroupPDIPPDIPSOICSOICSOICSOICSOICSOICSOSOTSSOP
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SO: 80 mm2: 7.8 x 10.2(SO)14SO: 80 mm2: 7.8 x 10.2(SO)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyCD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000CD4000
VCC(Max), V1818181818181818181818
VCC(Min), V33333333333
Voltage(Nom), V1010101010101010101010
tpd @ Nom Voltage(Max), ns130130130130130130130130130130130

Eco Plan

CD4077BECD4077BEE4CD4077BMCD4077BM96CD4077BM96E4CD4077BM96G4CD4077BME4CD4077BMTCD4077BNSRCD4077BNSRG4CD4077BPW
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

Application Notes

  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
    PDF, 188 Kb, File published: Dec 3, 2001
    Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, File published: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
  • Introduction to Logic
    PDF, 93 Kb, File published: Apr 30, 2015

Model Line

Manufacturer's Classification

  • Semiconductors > Logic > Gate > XNOR (Exclusive NOR) Gate
EMS supplier