Datasheet Texas Instruments CD74HCT75E
| Manufacturer | Texas Instruments |
| Series | CD74HCT75 |
| Part Number | CD74HCT75E |
High Speed CMOS Logic Dual 2-Bit Bistable Transparent Latch 16-PDIP -55 to 125
Datasheets
CD54HC75, CD74HC75, CD54HCT75, CD74HCT75 datasheet
PDF, 694 Kb, Revision: F, File published: Oct 13, 2003
Extract from the document
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | CD74HCT75E |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Download |
Parametrics
| 3-State Output | No |
| Bits | 4 |
| F @ Nom Voltage(Max) | 25 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Operating Temperature Range | -55 to 125 C |
| Output Drive (IOL/IOH)(Max) | 4/-4 mA |
| Package Group | PDIP |
| Package Size: mm2:W x L | See datasheet (PDIP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HCT |
| VCC(Max) | 5.5 V |
| VCC(Min) | 4.5 V |
| Voltage(Nom) | 5 V |
| tpd @ Nom Voltage(Max) | 35 ns |
Eco Plan
| RoHS | Compliant |
| Pb Free | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
Model Line
Series: CD74HCT75 (4)
- CD74HCT75E CD74HCT75EE4 CD74HCT75M CD74HCT75MG4
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > Other Latch