Datasheet Texas Instruments DAC5674

Manufacturer	Texas Instruments
Series	DAC5674

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Parametrics

Parameters / Models	DAC5674IPHP	DAC5674IPHPG4	DAC5674IPHPR
Architecture	Current Source	Current Source	Current Source
DAC Channels	1	1	1
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS
Interpolation	2x,4x	2x,4x	2x,4x
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85
Package Group	HTQFP	HTQFP	HTQFP
Package Size: mm2:W x L, PKG	48HTQFP: 81 mm2: 9 x 9(HTQFP)	48HTQFP: 81 mm2: 9 x 9(HTQFP)	48HTQFP: 81 mm2: 9 x 9(HTQFP)
Power Consumption(Typ), mW	435	435	435
Rating	Catalog	Catalog	Catalog
Resolution, Bits	14	14	14
SFDR, dB	76	76	76
Sample / Update Rate, MSPS	400	400	400

Eco Plan

Application Notes

• Download
  Interfacing op amps to high-speed DACs, Part 2: Current-sourcing DACs
  PDF, 617 Kb, File published: Oct 4, 2009
• Download
  Passive Terminations for Current Output DACs
  PDF, 244 Kb, File published: Nov 10, 2008
  The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
• Download
  Q4 2009 Issue Analog Applications Journal
  PDF, 1.5 Mb, File published: Oct 4, 2009
• Download
  Wideband Complementary Current Output DAC Single-Ended Interface
  PDF, 597 Kb, File published: Jun 21, 2005
  High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

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Manufacturer's Classification

• Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)