Datasheet Texas Instruments DAC5687

ManufacturerTexas Instruments
SeriesDAC5687
Datasheet Texas Instruments DAC5687

Dual-Channel, 16-Bit, 500-MSPS, 1x-8x Interpolating Digital-to-Analog Converter (DAC)

Datasheets

16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC datasheet
PDF, 2.7 Mb, Revision: E, File published: Sep 20, 2006
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Prices

Status

DAC5687IPZPDAC5687IPZPG4DAC5687IPZPR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoYes

Packaging

DAC5687IPZPDAC5687IPZPG4DAC5687IPZPR
N123
Pin100100100
Package TypePZPPZPPZP
Industry STD TermHTQFPHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY90901000
CarrierEIAJ TRAY (10+1)EIAJ TRAY (10+1)LARGE T&R
Device MarkingDAC5687IPZPDAC5687IPZPDAC5687IPZP
Width (mm)141414
Length (mm)141414
Thickness (mm)111
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical DataDownloadDownloadDownload

Parametrics

Parameters / ModelsDAC5687IPZP
DAC5687IPZP
DAC5687IPZPG4
DAC5687IPZPG4
DAC5687IPZPR
DAC5687IPZPR
ArchitectureCurrent SinkCurrent SinkCurrent Sink
DAC Channels222
InterfaceParallel CMOSParallel CMOSParallel CMOS
Interpolation1x,2x,4x,8x1x,2x,4x,8x1x,2x,4x,8x
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Package GroupHTQFPHTQFPHTQFP
Package Size: mm2:W x L, PKG100HTQFP: 256 mm2: 16 x 16(HTQFP)100HTQFP: 256 mm2: 16 x 16(HTQFP)100HTQFP: 256 mm2: 16 x 16(HTQFP)
Power Consumption(Typ), mW141014101410
RatingCatalogCatalogCatalog
Resolution, Bits161616
SFDR, dB808080
Sample / Update Rate, MSPS500500500

Eco Plan

DAC5687IPZPDAC5687IPZPG4DAC5687IPZPR
RoHSCompliantCompliantCompliant

Application Notes

  • DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)
    PDF, 686 Kb, Revision: A, File published: Jul 21, 2005
    DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes
  • Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
    PDF, 319 Kb, File published: Jul 14, 2009
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, File published: Nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • Q3 2009 Issue Analog Applications Journal
    PDF, 2.1 Mb, File published: Jul 14, 2009
  • High Speed Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, Revision: A, File published: Oct 23, 2012
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)
EMS supplier