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DS90LV110T
www.ti.com SNOS522I – JANUARY 2001 – REVISED APRIL 2013 DS90LV110T 1 to 10 LVDS Data/Clock Distributor
Check for Samples: DS90LV110T FEATURES DESCRIPTION DS90LV110 is a 1 to 10 data/clock distributor utilizing
LVDS (Low Voltage Differential Signaling) technology
for low power, high speed operation. Data paths are
fully differential from input to output for low noise
generation and low pulse width distortion. The design
allows connection of 1 input to all 10 outputs. LVDS
I/O enable high speed data transmission for point-topoint interconnects. This device can be used as a
high speed differential 1 to 10 signal distribution /
fanout replacing multi-drop bus applications for higher
speed links with improved signal quality. It can also
be used for clock distribution up to 400MHz. 1 2 Low jitter 800 Mbps fully differential data path
145 ps (typ) of pk-pk jitter with PRBS = 223-1
data pattern at 800 Mbps
Single +3.3 V Supply
Less than 413 mW (typ) total power dissipation
Balanced output impedance
Output channel-to-channel skew is 35ps (typ)
Differential output voltage (VOD) is 320mV (typ)
with 100О© termination load.
LVDS receiver inputs accept LVPECL signals
Fast propagation delay of 2.8 ns (typ) …
