Datasheet Texas Instruments OPA830

Manufacturer	Texas Instruments
Series	OPA830

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Parametrics

Parameters / Models	OPA830ID	OPA830IDBVR	OPA830IDBVRG4	OPA830IDBVT	OPA830IDBVTG4	OPA830IDG4	OPA830IDR	OPA830IDRG4
2nd Harmonic, dBc	67	67		67	67	67	67	67
2nd Harmonic(dBc)			67
3rd Harmonic, dBc	60	60		60	60	60	60	60
3rd Harmonic(dBc)			60
@ MHz	5	5	5	5	5	5	5	5
Acl, min spec gain, V/V	1	1		1	1	1	1	1
Acl, min spec gain(V/V)			1
Additional Features	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
Approx. Price (US$)			1.02 | 1ku
Architecture	Bipolar,Voltage FB	Bipolar,Voltage FB	Bipolar Voltage FB	Bipolar,Voltage FB	Bipolar,Voltage FB	Bipolar,Voltage FB	Bipolar,Voltage FB	Bipolar,Voltage FB
BW @ Acl, MHz	310	310		310	310	310	310	310
BW @ Acl(MHz)			310
CMRR(Min), dB	76	76		76	76	76	76	76
CMRR(Min)(dB)			76
CMRR(Typ), dB	80	80		80	80	80	80	80
CMRR(Typ)(dB)			80
GBW(Typ), MHz	310	310		310	310	310	310	310
GBW(Typ)(MHz)			310
Input Bias Current(Max), pA	10000000	10000000		10000000	10000000	10000000	10000000	10000000
Input Bias Current(Max)(pA)			10000000
Iq per channel(Max), mA	4.7	4.7		4.7	4.7	4.7	4.7	4.7
Iq per channel(Max)(mA)			4.7
Iq per channel(Typ), mA	4.25	4.25		4.25	4.25	4.25	4.25	4.25
Iq per channel(Typ)(mA)			4.25
Number of Channels	1	1		1	1	1	1	1
Number of Channels(#)			1
Offset Drift(Typ), uV/C	25	25		25	25	25	25	25
Offset Drift(Typ)(uV/C)			25
Operating Temperature Range, C	-40 to 85	-40 to 85		-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Operating Temperature Range(C)			-40 to 85
Output Current(Typ), mA	80	80		80	80	80	80	80
Output Current(Typ)(mA)			80
Package Group	SOIC	SOT-23	SOT-23	SOT-23	SOT-23	SOIC	SOIC	SOIC
Package Size: mm2:W x L, PKG	8SOIC: 29 mm2: 6 x 4.9(SOIC)	5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)		5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)	5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)	8SOIC: 29 mm2: 6 x 4.9(SOIC)
Package Size: mm2:W x L (PKG)			5SOT-23: 8 mm2: 2.8 x 2.9(SOT-23)
Rail-to-Rail	In to V-,Out	In to V-,Out	In to V- Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out	In to V-,Out
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Slew Rate(Typ), V/us	600	600		600	600	600	600	600
Slew Rate(Typ)(V/us)			600
Total Supply Voltage(Max), +5V=5, +/-5V=10	11	11		11	11	11	11	11
Total Supply Voltage(Max)(+5V=5, +/-5V=10)			11
Total Supply Voltage(Min), +5V=5, +/-5V=10	2.8	2.8		2.8	2.8	2.8	2.8	2.8
Total Supply Voltage(Min)(+5V=5, +/-5V=10)			2.8
Vn at 1kHz(Typ), nV/rtHz	9.5	9.5		9.5	9.5	9.5	9.5	9.5
Vn at Flatband(Typ), nV/rtHz	9.2	9.2		9.2	9.2	9.2	9.2	9.2
Vn at Flatband(Typ)(nV/rtHz)			9.2
Vos (Offset Voltage @ 25C)(Max), mV	7	7		7	7	7	7	7
Vos (Offset Voltage @ 25C)(Max)(mV)			7

Eco Plan

Application Notes

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  PDF, 219 Kb, Revision: A, File published: Jul 28, 2012
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  RLC Filter Design for ADC Interface Applications (Rev. A)
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  As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD
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  Wideband Complementary Current Output DAC Single-Ended Interface
  PDF, 597 Kb, File published: Jun 21, 2005
  High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
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  ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC Drivers
  PDF, 273 Kb, File published: Apr 22, 2004
  Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation
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  Measuring Board Parasitics in High-Speed Analog Design
  PDF, 134 Kb, File published: Jul 7, 2003
  Successful circuit designs using high-speed amplifiers can depend upon understanding and identifying parasitic PCB components. Simulating a design while including PCB parasitics can protect against unpleasant production surprises. This application report discusses an easy method for measuring parasitic components in a prototype or final PC board design by using a standard oscilloscope and low freq
• Download
  Noise Analysis for High Speed Op Amps (Rev. A)
  PDF, 256 Kb, Revision: A, File published: Jan 17, 2005
  As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

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Manufacturer's Classification

• Semiconductors> Amplifiers> Operational Amplifiers (Op Amps)> High-Speed Op Amps (>=50MHz)