Datasheet Texas Instruments SN74LS51

Manufacturer	Texas Instruments
Series	SN74LS51

2-Wide 2-Input and 2-Wide 3-Input AND-OR-Invert Gates

Datasheets

PDF, 1.1 Mb, File published: Mar 1, 1988

Extract from the document

	SN74LS51D	SN74LS51DR	SN74LS51N	SN74LS51NSR
Lifecycle Status	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No

	SN74LS51D	SN74LS51DR	SN74LS51N	SN74LS51NSR
N	1	2	3	4
Pin	14	14	14	14
Package Type	D	D	N	NS
Industry STD Term	SOIC	SOIC	PDIP	SOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDIP-T	R-PDSO-G
Package QTY	50	2500	25	2000
Carrier	TUBE	LARGE T&R	TUBE	LARGE T&R
Device Marking	LS51	LS51	SN74LS51N	74LS51
Width (mm)	3.91	3.91	6.35	5.3
Length (mm)	8.65	8.65	19.3	10.3
Thickness (mm)	1.58	1.58	3.9	1.95
Pitch (mm)	1.27	1.27	2.54	1.27
Max Height (mm)	1.75	1.75	5.08	2
Mechanical Data	Download	Download	Download	Download

Parameters / Models	SN74LS51D	SN74LS51DR	SN74LS51N	SN74LS51NSR
Bits	2	2	2	2
F @ Nom Voltage(Max), Mhz	35	35	35	35
ICC @ Nom Voltage(Max), mA	0.014	0.014	0.014	0.014
Operating Temperature Range, C	0 to 70	0 to 70	0 to 70	0 to 70
Output Drive (IOL/IOH)(Max), mA	0.4/-16	0.4/-16	0.4/-16	0.4/-16
Package Group	SOIC	SOIC	PDIP	SO
Package Size: mm2:W x L, PKG	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	See datasheet (PDIP)	14SO: 80 mm2: 7.8 x 10.2(SO)
Rating	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No
Technology Family	LS	LS	LS	LS
VCC(Max), V	5.25	5.25	5.25	5.25
VCC(Min), V	4.75	4.75	4.75	4.75
Voltage(Nom), V	5	5	5	5
tpd @ Nom Voltage(Max), ns	20	20	20	20

	SN74LS51D	SN74LS51DR	SN74LS51N	SN74LS51NSR
RoHS	Compliant	Compliant	Compliant	Compliant
Pb Free	Yes

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Designing with the SN54/74LS123 (Rev. A)
PDF, 118 Kb, Revision: A, File published: Mar 1, 1997
The Texas Instruments (TI) SN54/74LS123 dual retriggerable monostable multivibrator is a one-shot device capable of verylong output pulses and up to 100% duty cycle. The ?LS123 also features dc triggering from gated low-level active A andhigh-level active B inputs and provides a clear input that terminates the output pulse of any predetermined time independentof timing components R ext and

Series: SN74LS51 (4)