Datasheet Texas Instruments SN74LVT182502PM
| Manufacturer | Texas Instruments |
| Series | SN74LVT182502 |
| Part Number | SN74LVT182502PM |
3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers 64-LQFP -40 to 85
Datasheets
3.3-V ABT Scan Test Devices With 18-Bit Universal Bus Transceivers (Rev. F)
PDF, 504 Kb, Revision: F, File published: Jul 1, 1996
Prices
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 64 |
| Package Type | PM |
| Industry STD Term | LQFP |
| JEDEC Code | S-PQFP-G |
| Width (mm) | 10 |
| Length (mm) | 10 |
| Thickness (mm) | 1.4 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.6 |
| Mechanical Data | Download |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Application Notes
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
Model Line
Series: SN74LVT182502 (1)
- SN74LVT182502PM
Manufacturer's Classification
- Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic
