Datasheet Texas Instruments TMS320C6678

ManufacturerTexas Instruments
SeriesTMS320C6678
Datasheet Texas Instruments TMS320C6678

Multicore Fixed and Floating-Point Digital Signal Processor

Datasheets

TMS320C6678 Multicore Fixed and Floating-Point Digital Signal Processor datasheet
PDF, 2.2 Mb, Revision: E, File published: Mar 6, 2014
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Prices

Status

TMS320C6678ACYPTMS320C6678ACYP25TMS320C6678ACYP4TMS320C6678ACYPATMS320C6678ACYPA25TMS320C6678AGYPATMS320C6678AXCYPTMS320C6678AXCYP25TMS320C6678AXCYPA
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoNoNoNoYesNoYesYes

Packaging

TMS320C6678ACYPTMS320C6678ACYP25TMS320C6678ACYP4TMS320C6678ACYPATMS320C6678ACYPA25TMS320C6678AGYPATMS320C6678AXCYPTMS320C6678AXCYP25TMS320C6678AXCYPA
N123456789
Pin841841841841841841841841841
Package TypeCYPCYPCYPCYPCYPGYPCYPCYPCYP
Package QTY444444444444444444
CarrierJEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)JEDEC TRAY (5+1)
Device Marking@2010 TI1.25GHZTMS320C6678CYPTMS320C6678CYP@2010 TIA@2010 TI@2010 TIA
Width (mm)242424242424242424
Length (mm)242424242424242424
Thickness (mm)2.822.822.822.822.822.812.822.822.82
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsTMS320C6678ACYP
TMS320C6678ACYP
TMS320C6678ACYP25
TMS320C6678ACYP25
TMS320C6678ACYP4
TMS320C6678ACYP4
TMS320C6678ACYPA
TMS320C6678ACYPA
TMS320C6678ACYPA25
TMS320C6678ACYPA25
TMS320C6678AGYPA
TMS320C6678AGYPA
TMS320C6678AXCYP
TMS320C6678AXCYP
TMS320C6678AXCYP25
TMS320C6678AXCYP25
TMS320C6678AXCYPA
TMS320C6678AXCYPA
ApplicationsCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and TelecomCommunications and Telecom
DRAMDDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3DDR3
DSP8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x8 C66x
DSP MHz, Max.1000,12501000,12501000,12501000,12501000,12501000,12501000,12501000,12501000,1250
EMAC2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch2-Port 1Gb Switch
GFLOPS128,160128,160128,160128,160128,160128,160128,160128,160128,160
On-Chip L2 Cache4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB
Operating Temperature Range, C-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85-40 to 100,0 to 85
Other On-Chip Memory4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB4096 KB
PCI/PCIe2 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen22 PCIe Gen2
Package Size: mm2:W x L, PKGSee datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)See datasheet (FCBGA)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Serial I/OI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UARTI2C,RapidIO,SPI,TSIP,UART
Serial RapidIO1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)1 (four lanes)
Total On-Chip Memory, KB883288328832883288328832883288328832

Eco Plan

TMS320C6678ACYPTMS320C6678ACYP25TMS320C6678ACYP4TMS320C6678ACYPATMS320C6678ACYPA25TMS320C6678AGYPATMS320C6678AXCYPTMS320C6678AXCYP25TMS320C6678AXCYPA
RoHSCompliantCompliantCompliantCompliantCompliantSee ti.comCompliantCompliantCompliant

Application Notes

  • PCI Express (PCIe) Resource Wiki for Keystone Devices (Rev. A)
    PDF, 57 Kb, Revision: A, File published: May 19, 2017
  • Keystone NDK FAQ
    PDF, 54 Kb, File published: Oct 3, 2016
    This document is a collection of frequently asked questions (FAQ) on running the NDK examples on the KeyStoneв„ў family of devices.
  • TI Keystone DSP Hyperlink SerDes IBIS-AMI Models
    PDF, 3.2 Mb, File published: Oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP Hyperlink interface.
  • TI Keystone DSP PCIe SerDes IBIS-AMI Models
    PDF, 4.8 Mb, File published: Oct 9, 2014
    This document describes the organization, structure, and proper usage of the TI serializer and deserializer (SerDes) IBIS-AMI models for Keystone DSP PCIe interface.
  • SerDes Implementation Guidelines for KeyStone I Devices
    PDF, 590 Kb, File published: Oct 31, 2012
    The goal of KeyStone I SerDes collateral material is to make system implementation easier for the customer by providing the system solution. For these SerDes-based interfaces, it is not assumed that the system designer is familiar with the industry specifications, SerDes technology, or RF/microwave PCB design. However, it is still expected that the PCB design work will be supervised by a knowledge
  • Hardware Design Guide for KeyStone Devices (Rev. C)
    PDF, 1.7 Mb, Revision: C, File published: Sep 15, 2013
  • KeyStone I DDR3 Initialization (Rev. E)
    PDF, 114 Kb, Revision: E, File published: Oct 28, 2016
    The initialization of the DDR3 DRAM controller on KeyStone I DSPs is straightforward as long as the proper steps are followed. However, if some steps are omitted or if some sequence-sensitive steps are implemented in the wrong order, DDR3 operation will be unpredictable.All DDR3 initialization routines must contain the basic register writes to configure the memory controller within the DSP
  • TMS320C66x DSP Generation of Devices (Rev. A)
    PDF, 245 Kb, Revision: A, File published: Apr 25, 2011
  • AN-1281 Bumped Die (Flip Chip) Packages (Rev. A)
    PDF, 2.2 Mb, Revision: A, File published: May 1, 2004
    Application Note 1281 Bumped Die (Flip Chip) Packages
  • SERDES Link Commissioning on KeyStone I and II Devices
    PDF, 138 Kb, File published: Apr 13, 2016
    The serializer-deserializer (SerDes) performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. This application report explains the SerDes transmit and receive parameters tuning, tools and some debug techniques for TI Keystone I and Keystone II devices.
  • PCIe Use Cases for KeyStone Devices
    PDF, 320 Kb, File published: Dec 13, 2011
  • Clocking Design Guide for KeyStone Devices
    PDF, 1.5 Mb, File published: Nov 9, 2010
  • Optimizing Loops on the C66x DSP
    PDF, 585 Kb, File published: Nov 9, 2010
  • The C6000 Embedded Application Binary Interface Migration Guide (Rev. A)
    PDF, 20 Kb, Revision: A, File published: Nov 10, 2010
    The C6000 compiler tools support a new ELF-based ABI named EABI. Prior to this time, the compiler only supported a single ABI, which is now named COFF ABI. The following compelling best-in-class features are available under the C6000 EABI:GeneralZero-init globals: “int gvar;” gets set to 0 before main runs.Dynamic linking: Add code to a running system.Native ROM
  • DDR3 Design Requirements for KeyStone Devices (Rev. B)
    PDF, 582 Kb, Revision: B, File published: Jun 5, 2014
  • Multicore Programming Guide (Rev. B)
    PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
    As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
  • TI DSP Benchmarking
    PDF, 62 Kb, File published: Jan 13, 2016
    This application report provides benchmarks for the C674x DSP core, the C66x DSP core and the ARMВ®CortexВ®-A15 core. This document also shows how to reproduce these benchmarks on specific hardware platforms.
  • Thermal Design Guide for DSP and ARM Application Processors (Rev. A)
    PDF, 324 Kb, Revision: A, File published: Aug 17, 2016
    This application report has been compiled to provide specific information and considerations regarding thermal design requirements for all DSP and ARM-based single and multi-core processors (collectively referred to as “processors”, “System-on-chip”, or “SoC”). The information contained within this document is intended to provide a minimum level of understanding with regards to the thermal require
  • Plastic Ball Grid Array [PBGA] Application Note (Rev. B)
    PDF, 1.6 Mb, Revision: B, File published: Aug 13, 2015

Model Line

Manufacturer's Classification

  • Semiconductors> Processors> Digital Signal Processors> C6000 DSP> C66x DSP
EMS supplier