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Datasheet Linear Technology LTC2270

ManufacturerLinear Technology
SeriesLTC2270

16-Bit, 20Msps Low Noise Dual ADC

Datasheets

  • Download » Datasheet PDF, 593 Kb, File uploaded: Jul 31, 2016
    LTC2270 - 16-Bit, 20Msps Low Noise Dual ADC
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    LTC2270
    16-Bit, 20Msps
    Low Noise Dual ADC
    FEATURES DESCRIPTION n The LTCВ®2270 is a two-channel simultaneous sampling
    16-bit A/D converter designed for digitizing high frequency,
    wide dynamic range signals. It is perfect for demanding
    applications with AC performance that includes 84.1dB
    SNR and 99dB spurious free dynamic range (SFDR). n n Two-Channel Simultaneously Sampling ADC
    84.1dB SNR (46ОјVRMS Input Referred Noise)
    99dB SFDR
    В±2.3LSB INL(Max)
    Low Power: 160mW Total, 80mW per Channel
    Single 1.8V Supply
    CMOS, DDR CMOS, or DDR LVDS Outputs
    Selectable Input Ranges: 1VP-P to 2.1VP-P
    200MHz Full Power Bandwidth S/H
    Shutdown and Nap Modes
    Serial SPI Port for Configuration
    Pin Compatible with
    LTC2180: 16-Bit, 25Msps, 78mW
    LTC2140-14: 14-Bit, 25Msps, 50mW
    64-Lead (9mm Г— 9mm) QFN Package DC specs include В±1LSB INL (typ), В±0.2LSB DNL (typ)
    and no missing codes over temperature. The transition ...

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Packaging

Parametrics

LTC2270CUP#PBFLTC2270CUP#TRPBFLTC2270IUP#PBFLTC2270IUP#TRPBF
ADC INL, LSB1111
ADCs2222
ArchitecturePipelinePipelinePipelinePipeline
Bipolar/Unipolar InputBipolarBipolarBipolarBipolar
Bits, bits16161616
Number of Channels2222
DNL, LSB0.20.20.20.2
Demo BoardsDC1620A-T,DC1975A-ADC1620A-T,DC1975A-ADC1620A-T,DC1975A-ADC1620A-T,DC1975A-A
Design ToolsLinearLabToolsLinearLabToolsLinearLabToolsLinearLabTools
Export Controlnononono
FeaturesSimultaneous Sampling, Clock Duty Cycle Stabilizer, Data Output RandomizerSimultaneous Sampling, Clock Duty Cycle Stabilizer, Data Output RandomizerSimultaneous Sampling, Clock Duty Cycle Stabilizer, Data Output RandomizerSimultaneous Sampling, Clock Duty Cycle Stabilizer, Data Output Randomizer
I/OParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDSParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDSParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDSParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDS
Input DriveDifferentialDifferentialDifferentialDifferential
Input Span1Vpp to 2.1Vpp1Vpp to 2.1Vpp1Vpp to 2.1Vpp1Vpp to 2.1Vpp
Internal Referenceyesyesyesyes
Latency6666
Operating Temperature Range, °C0 to 700 to 70-40 to 85-40 to 85
Power, mW160160160160
SFDR, dB99999999
SINAD, dB83.983.983.983.9
SNR, dB84.184.184.184.1
Simultaneousyesyesyesyes
Speed, ksps20000200002000020000
Supply Voltage Range1.8V1.8V1.8V1.8V

Eco Plan

LTC2270CUP#PBFLTC2270CUP#TRPBFLTC2270IUP#PBFLTC2270IUP#TRPBF
RoHSCompliantCompliantCompliantCompliant

Design Notes

  • Download » Design Notes - DN1031 PDF, 649 Kb, File published: Jun 21, 2013
    Interfacing to High Performance Pipeline ADCs
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    Interfacing to High Performance Pipeline ADCs
    Design Note 1031
    Tyler Hutchison and Clarence Mayott Introduction
    High speed ADCs use a sample and hold input structure comprising a fast CMOS switch and a sampling
    capacitor. When the CMOS switch closes, the sampling
    capacitor shares its stored charge with the preceding
    drive circuitry (charge kickback). As the sampling
    capacitor and its stored charge increase in size, more
    attention must be paid to the drive circuitry.
    Pipeline ADCs typically have a few picofarads of
    sample capacitance. In contrast, the high performance
    16-bit 20Msps LTC В®2270 high speed ADC uses a 17pF
    sampling capacitor. The advantage of a relatively large
    sampling capacitor is a significant reduction of internal
    kT/C noise and therefore better signal-to-noise ratio
    (SNR). The disadvantage is that the part becomes more
    difficult to drive. Every time the CMOS switch closes,
    the sampling capacitor kicks back significantly more
    charge to the driver than would a smaller sampling
    capacitor.
    The interface filter, between the driver and ADC,
    demands extra attention. An inappropriate filter de-R14
    35.7О© L5 ...

Articles

  • Download » Articles - LT Journal PDF, 4.7 Mb, File published: Jul 9, 2013
    Near Noiseless ADC Drivers for Imaging
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    design ideas Near Noiseless ADC Drivers for Imaging
    Derek Redmayne CCDs (charge coupled devices) and other sensors place heavy demands on digitizers,
    both in terms of sample rates, and in signal-to-noise ratio. The sensor output is typically
    a ground-referenced series of analog levels (pixels), possibly with transients occurring
    between the pixel boundaries. As the number of pixels increases, so does the sample
    rate of the ADC required to capture the image, with 20Msps pipelined ADCs sufficient for
    most high dynamic range applications. To ensure the highest SNR performance of the
    sampled signal, the drive circuitry for the ADC must provide low impedance, fast settling
    without introducing wideband noise and yet present high input impedance to the sensor.
    This article presents an interface circuit
    between the sensor and a high performance ADC that does not compromise
    the SNR performance. The LTC2270
    16-bit pipelined ADC family is intended
    for high end imaging applications. The
    84.1dB SNR of this family makes it attractive for imaging, but it also features
    very good SFDR—over 100dB. The input
    range is 2.1VP–P, significantly less than
    the output of most imaging devices, so
    attenuation and level-shifting is required.
    The inputs of these ADCs must be driven
    with a well-balanced differential drive. The
    single ended drive normally available from
    the sensor would force the internal virtual ...

Moldel Line

Series: LTC2270 (4)

Manufacturer's Classification

  • Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)

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