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LTC2414 LTC2414

Application Notes

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  Delta Sigma ADC Bridge Measurement Techniques &mdash AN96
  PDF, 232 Kb, File published: Jan 17, 2005
  AN96 features several applications that demonstrate how to take full advantage of Linear Technology's delta sigma ADCs when interfacing to sensors. In many cases, signal conditioning can be greatly simplified or eliminated completely. This note explains where it is appropriate to use amplifiers and how to optimize amplifier gain. Also included are discussions on measuring effective number of bits (ENOB) and the relationship to instrument performance, frequency response of delta sigma ADCs, and test techniques. C source code for all of the applications is included to aid firmware development.
  Extract from the document

  Application Note 96
  January 2005
  Delta Sigma ADC Bridge Measurement Techniques
  Mark Thoren
  Introduction In a typical 12-bit measurement system, the signal conditioning amplifier requires a very high gain in order to make
  use of the full ADC input range. A sensor with a 10mV fullscale output requires a gain of 500 to use the full input
  range of a typical 5V input ADC. A filter may be required to
  reduce noise at the expense of settling time. Additional
  difficulties arise when dealing with the large common
  mode voltage typical of a bridge sensor. Most instrumentation amplifiers have a large discrepancy between the
  typical CMRR and guaranteed minimum, which may require an additional trim. Sensors for pressure, load, temperature, acceleration and
  many other physical quantities often take the form of a
  Wheatstone bridge. These sensors can be extremely linear
  and stable over time and temperature. However, most
  things in nature are only linear if you don’t bend them too
  much. In the case of a load cell, Hooke’s law states that the
  strain in a material is proportional to the applied stress—
  as long as the stress is nowhere near the material’s yield
  point (the “point of no return” where the material is
  permanently deformed). The consequence is that a load
  cell based on a resistance strain gauge will have a very
  small electrical output—often only a few millivolts. In
  spite of this, instruments with 100,000 counts of resolution and more are possible. This Application Note presents …

Design Notes

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  16-Channel, 24-Bit О”ОЈ ADC Provides Small, Flexible and Accurate Solutions for Data Acquisition &mdash DN297
  PDF, 106 Kb, File published: Oct 2, 2002
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  16-Channel, 24-Bit ∆Σ ADC Provides Small, Flexible and
  Accurate Solutions for Data Acquisition
  Design Note 297
  Sean Wang
  Introduction
  The LTC ®2418 is a new 16-channel No Latency ∆Σ™
  ADC that addresses applications where a variety of
  sensors are monitored. The input can be configured as
  16 single-ended, eight differential, or any combination
  of differential and single-ended channels to fit the end
  application. Furthermore, the polarity of a differential
  channel can be reversed. Each selection maintains the
  excellent performance of the core 24-bit ADC, has a
  full-scale differential input range of –1/2VREF to 1/2VREF
  and the input common mode can be anywhere within
  GND and VCC with DC common mode input rejection
  better than 140dB.
  The converter has an on-chip oscillator that requires
  no external frequency setting components. Through a
  single pin, the LTC2418 can provide better than 110dB
  differential mode rejection at 50Hz or 60Hz В±2%. The
  LTC2418 communicates through a flexible 4-wire SPI digital interface. No extra register configuration is
  required except the channel address. …

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  Powering Altera Arria 10 FPGA and Arria 10 SoC: Tested and Verified Power Management Solutions &mdash DN549
  PDF, 1.6 Mb, File published: Feb 19, 2016
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  Powering Altera ArriaВ 10 FPGA andВ Arria 10 SoC: Tested
  and Verified Power Management Solutions
  Design Note 549
  Afshin Odabaee
  Introduction
  FPGA development kits allow system developers to
  evaluate an FPGA without having to design a complete
  system. Figures 1 and 2 show Altera’s new 20nm
  Arria 10 FPGAs and Arria 10В SoCs (System-on-Chip)
  development boards. These boards are tested and
  verified by Altera, exemplifying best design practices
  in layout, signal integrity and power management.
  Power Management for Core, System and I/O
  The power management solution for high end FPGAs,
  including the Arria 10, should be carefully selected.
  A well thought-out power management design can
  reduce PCB size, weight and complexity, as well as
  lower power consumption and cooling costs. And it
  is essential to achieve optimal system performance.
  ForВ example, the 0.95V at 105A supplied by the 12V
  DC/DC regulator powering the core of the Arria 10 GX
  FPGA in Figure 1 has several features that complement
  the power saving schemes of the SoC: Figure 1. Arria 10 GX FPGA Development Kit …

Articles

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  Avoid Debugging Cycles in Power Management for FPGA, GPU and ASIC Systems &mdash LT Journal
  PDF, 3.2 Mb, File published: Aug 25, 2016
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  Avoid Debugging Cycles in Power Management for FPGA,
  GPU and ASIC Systems
  Afshin Odabaee When it comes to designing FPGA, GPU or ASIC controlled systems, the number of
  design challenges related to power management and analog systems pale in comparison
  to those related to digital design. Nevertheless, it is risky to assume that power system
  design can be left to “later,” or taken in line with digital design. Even seemingly innocuous
  problems in power supply design can significantly delay the release of a system, as any
  added time to the power system debugging cycle can halt all work on the digital side.
  A good way to put DC/DC regulation
  issues to rest is to use a verified development kit offered by the FPGA, GPU or
  ASIC vendor. Often, the design itself or
  a similar design is available as a board/
  kit by the suppliers of power products
  and FPGA, GPU and ASIC manufacturers. Using a tested and verified kit unburdens
  system designers of most power system
  and analog issues, allowing them instead
  to focus their energies on configuring the
  complex digital systems. The optimum
  power system layout is taken care of
  before significant design is undertaken. THOUGHTFUL POWER MANAGEMENT
  IS CHALLENGING AT THE START Every design task is initially daunting,
  and power management design is no
  exception. This is the case when power is …

Model Line

Manufacturer's Classification

• Data Conversion > Analog-to-Digital Converters (ADC) > Precision ADCs (Fs < 10Msps) > Multi Channel ADCs