Datasheet Linear Technology LTC1661

Manufacturer	Linear Technology
Series	LTC1661

Micropower Dual 10-Bit DAC in MSOP

Datasheets

PDF, 245 Kb, Revision: B, File uploaded: Aug 22, 2017

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Prices

Packaging

	LTC1661CMS8#PBF	LTC1661CMS8#TRPBF	LTC1661CN8#PBF	LTC1661IMS8#PBF	LTC1661IMS8#TRPBF	LTC1661IN8#PBF
N	1	2	3	4	5	6
Package	MS-8 Package Outline Drawing	MS-8 Package Outline Drawing	N-8 Package Outline Drawing	MS-8 Package Outline Drawing	MS-8 Package Outline Drawing	N-8 Package Outline Drawing
Package Code	MS8	MS8	N	MS8	MS8	N
Package Index	05-08-1660	05-08-1660	05-08-1510 (N8)	05-08-1660	05-08-1660	05-08-1510 (N8)
Pin Count	8	8	8	8	8	8

Parametrics

Parameters / Models	LTC1661CMS8#PBF	LTC1661CMS8#TRPBF	LTC1661CN8#PBF	LTC1661IMS8#PBF	LTC1661IMS8#TRPBF	LTC1661IN8#PBF
Bits, bits	10	10	10	10	10	10
DAC INL, LSB	0.4	0.4	0.4	0.4	0.4	0.4
DACs	2	2	2	2	2	2
DNL, LSB	0.1	0.1	0.1	0.1	0.1	0.1
Export Control	no	no	no	no	no	no
Ext Vref Range	0V to VCC	0V to VCC	0V to VCC	0V to VCC	0V to VCC	0V to VCC
I/O	Serial SPI	Serial SPI	Serial SPI	Serial SPI	Serial SPI	Serial SPI
Max Gain Error, % FSR	1.17	1.17	1.17	1.17	1.17	1.17
Max Offset Error, mV	30	30	30	30	30	30
Operating Temperature Range, °C	0 to 70	0 to 70	0 to 70	-40 to 85	-40 to 85	-40 to 85
Output	Voltage	Voltage	Voltage	Voltage	Voltage	Voltage
Output Range	0V to VREF	0V to VREF	0V to VREF	0V to VREF	0V to VREF	0V to VREF
Power, mW	0.29	0.29	0.29	0.29	0.29	0.29
Power-On-Reset	Zero-Scale	Zero-Scale	Zero-Scale	Zero-Scale	Zero-Scale	Zero-Scale
Settling Time, µs	30	30	30	30	30	30
Supply Voltage Range	2.7V to 5.5V	2.7V to 5.5V	2.7V to 5.5V	2.7V to 5.5V	2.7V to 5.5V	2.7V to 5.5V

Eco Plan

	LTC1661CMS8#PBF	LTC1661CMS8#TRPBF	LTC1661CN8#PBF	LTC1661IMS8#PBF	LTC1661IMS8#TRPBF	LTC1661IN8#PBF
RoHS	Compliant	Compliant	Compliant	Compliant	Compliant	Compliant

Articles

Download
Dual 60uA 10-Bit Serial DAC in MS-8 Saves Power and Space &mdash LT Journal
PDF, 157 Kb, File published: Nov 1, 2000
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DESIGN INFORMATION Dual 60ВµA 10-Bit Serial DAC in MS-8
Saves Power and Space
by Vic Schrader
Introduction
DACs; the data path is double buffered to allow for simultaneous
updates. The digital inputs have
internal Schmitt triggers, which eliminate the need for external Schmitts
when the input signals are slow or
noisy, such as when using optoisolators. The block diagram of the
LTC1661 is shown in Figure 1. 3
2.9 VREF = VCC
CODE = 512 2.8 VCC = 5.5V 2.7 VOUT (V) The LTC1661 is a dual, serially
addressable 10-bit, rail-to-rail voltage output DAC with Sleep mode.
Operating on a single 2.7VвЂ“5.5V supply rail, its small size and low power
consumption make it most appropriate for use in products with stringent
space and/or power constraints. In
the 8-lead MSOP package, it occupies
just 0.02in2 of board space, 50% less
area than a standard SO-8 package;
each buffered DAC draws just 60ВµA
of supply current at 5V (48ВµA at 3V).
Sleep mode operation further reduces
total supply-plus-reference current …

Model Line

Series: LTC1661 (6)

LTC1661CMS8#PBF LTC1661CMS8#TRPBF LTC1661CN8#PBF LTC1661IMS8#PBF LTC1661IMS8#TRPBF LTC1661IN8#PBF

Manufacturer's Classification

Data Conversion > Digital-to-Analog Converters (DAC) > Voltage Output DACs | Unipolar Digital-to-Analog Converters (DAC)

EMS supplier

Slices

Microcontrollers