Datasheet Texas Instruments 74SSTUB32866AZKER
Manufacturer | Texas Instruments |
Series | 74SSTUB32866A |
Part Number | 74SSTUB32866AZKER |

25-Bit Configurable Registered Buffer w/Address-Parity Test 96-LFBGA -40 to 85
Datasheets
25-Bit Configurable Registered Buffer w/Address-Parity Test datasheet
PDF, 1.9 Mb, Revision: A, File published: Nov 1, 2007
Extract from the document
Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
Pin | 96 |
Package Type | ZKE |
Industry STD Term | BGA MICROSTAR |
JEDEC Code | R-PBGA-N |
Package QTY | 1000 |
Carrier | LARGE T&R |
Device Marking | SB866A |
Width (mm) | 5.5 |
Length (mm) | 13.5 |
Thickness (mm) | .85 |
Pitch (mm) | .8 |
Max Height (mm) | 1.4 |
Mechanical Data | Download |
Parametrics
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | N/A ps |
Function | DDR2 Register |
Number of Outputs | 25 |
Operating Frequency Range(Max) | 410 MHz |
Operating Temperature Range | -40 to 85 C |
Output Drive | 8 mA |
Package Group | LFBGA |
Package Size: mm2:W x L | 96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA) PKG |
Rating | Catalog |
VCC | 1.8 V |
t(phase error) | N/A ps |
tsk(o) | N/A ps |
Eco Plan
RoHS | Compliant |
Application Notes
- DDR2 Memory Interface Clocks and Registers - OverviewPDF, 308 Kb, File published: Mar 25, 2009
This application report gives an overview of the existing JEDEC DDR2 Register and PLL Buffer specifications and compliant TI devices.
Model Line
Series: 74SSTUB32866A (1)
- 74SSTUB32866AZKER
Manufacturer's Classification
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers