Datasheet Microchip TP2535
| Manufacturer | Microchip | 
| Series | TP2535 | 
This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and well-proven, silicon-gate manufacturing process
Datasheets
TP2535 Datasheet - P-Channel Enhancement-Mode Vertical DMOS FET
PDF, 612 Kb, Revision: 06-27-2014
Extract from the document
Status
| TP2535N3-G | |
|---|---|
| Lifecycle Status | Production (Appropriate for new designs but newer alternatives may exist) | 
Packaging
| TP2535N3-G | |
|---|---|
| N | 1 | 
| Package | TO-92 | 
| Pins | 3 | 
Parametrics
| Parameters / Models | TP2535N3-G | 
|---|---|
| BVdss min, V | -350 | 
| CISSmax, pF | 125 | 
| Operating Temperature Range, °C | -55 to +150 | 
| Rds, on) max | 25 | 
| Vgs(th) max, V | -2.4 | 
Eco Plan
| TP2535N3-G | |
|---|---|
| RoHS | Compliant | 
Model Line
Series: TP2535 (1)