Datasheet Linear Technology LTC6951

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LTC6951-1

Application Notes

• Download
  LTC6951 Synchronization Manual Design Examples for EZSync, ParallelSync, EZParallelSync and EZ204Sync &mdash AN161
  PDF, 6.3 Mb, File published: Mar 15, 2017
  Extract from the document

  Application Note 161
  March 2017
  LTC6951 Synchronization Manual
  Design Examples for EZSync, ParallelSync,
  EZParallelSync and EZ204Sync
  Chris Pearson Introduction For systems demanding a large number of synchronized
  clock signals, a clock tree using multiple clock devices
  is often required. Multiple clock devices can add system
  complexity when compared to a single clock distribution
  device. One complexity created is the ability to synchronize
  the clock phases and start times across multiple clock
  devices. The other challenge created is maintaining the
  desired low jitter clock performance when cascading
  multiple clock devices.
  Linear Technology’s family of PLL/VCO and clock distribution ICs address both the synchronization and performance concerns by providing three multichip synchronization
  options: EZSyncв„ў, ParallelSyncв„ў, and EZParallelSyncв„ў/
  EZ204Syncв„ў. This application note provides step by
  step design examples for each multichip synchronization
  method.
  Table 1 provides a summarized comparison of each
  synchronization method. Application Note 165 provides
  detailed descriptions and trade-offs of each synchronization
  method. …

• Download
  Multi-Part Clock Synchronization Methods for Large Data Acquisition Systems &mdash AN165
  PDF, 1.2 Mb, File published: Apr 4, 2017
  Extract from the document

  Application Note 165
  September 2017
  Multi-Part Clock Synchronization Methods for Large
  Data Acquisition Systems
  Doug La Porte
  Introduction
  High speed data conversion systems requiring a large
  number of low jitter clock signals often need to use multiple clocking devices. Compared to a clocking architecture
  requiring only a single clocking device, an architecture
  utilizing multiple devices complicates the system design
  in two major respects. First, these multiple devices must
  be synchronized to assure consistent clock phasing at all
  outputs. Second, maintaining low jitter is difficult as every
  device in the clocking system adds more noise. Designing
  a synchronized clocking system with both low jitter and a
  large number of outputs is a challenge.
  Fortunately, Linear Technology’s family of frequency
  synthesizers and clock distribution products addresses
  these concerns. For the purpose of this application note,
  it is convenient to sort all parts in the product family into
  PLL WITH DIVIDERS
  AND DISTRIBUTION
  (PLL+DIST) REFERENCE …

Articles

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  Multi-Output Clock Synthesizer with Integrated VCO Features the Low Jitter Required to Drive Modern High Speed ADC and DAC Clock Inputs &mdash LT Journal
  PDF, 672 Kb, File published: Apr 14, 2016
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  Multi-Output Clock Synthesizer with Integrated VCO Features
  the Low Jitter Required to Drive Modern High Speed ADC
  and DAC Clock Inputs
  Chris Pearson The latest high performance ADCs cannot realize their
  potential without an ultralow jitter high speed clock signal.
  The LTC6951 satisfies the requirements of top ADCs by
  producing a clock signal up to 2.7GHz with an impressively
  low wideband noise floor. Figure 1 compares the LTC6951’s
  measured ADC SNR results to other ADC clock sources.
  The quantity and performance requirements for low jitter clocks in electronic
  systems continues to increase with system
  complexity and performance. This may
  result in a costly array of parts, including
  VCOs, PLLs, clock distribution devices and
  synchronization components to support
  the clock signals. The LTCВ®6951, on the
  other hand, decreases complexity and cost
  by integrating a high performance PLL/
  VCO, and distributing five ultralow jitter
  clock outputs. Additionally, the LTC6951
  supports several software-based synchronization methods: EZSyncв„ў, ParallelSyncв„ў
  and EZ204Syncв„ў (aka EZParallelSyncв„ў). The latest trend in high speed converter
  digital interfaces is the adoption of the …

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Manufacturer's Classification

• Timing > PLL Synthesizers & VCOs > PLL With Integrated VCOs | Integer-N PLLs
• Timing > Clock Generation and Distribution > Clock Generation