Datasheet Analog Devices AD9508BCPZ

1.65 GHz Clock Fanout Buffer with
Output Dividers and Delay Adjust
AD9508 Data Sheet FUNCTIONAL BLOCK DIAGRAM 1.65 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers
Up to 4 differential outputs or 8 CMOS outputs
Pin strapping capability for hardwired programming at
power-up 1 V/ns, unless otherwise noted. POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE Min
2.375 CURRENT CONSUMPTION
LVDS Configuration HSTL Configuration CMOS Configuration Full Power-Down
TEMPERATURE
Ambient Temperature Range, TA
Junction Temperature, TJ −40 Typ
2.5 Max
3.465 Unit
V Test Conditions/Comments
Use supply voltage setting (2.5 V or 3.3 V) and
appropriate current consumption configuration
(see Current Consumption parameters in Table 1)
to calculate total power dissipation 165 182 mA 122 134 mA 194 213 mA 131 144 mA 92 101 mA 141 185 mA 122 134 mA 85 94 mA Input clock: 1500 MHz in differential mode, all
LVDS output drivers at 1500 MHz …

1.2 GHz Clock Fanout Buffer
with Output Dividers and Delay
AD9508-EP Enhanced Product
FEATURES GENERAL DESCRIPTION 1.2 GHz differential clock inputs/outputs
10-bit programmable dividers, 1 to 1024, all integers
Up to 4 differential outputs or 8 CMOS outputs
Pin strapping mode for hardwired programming at power-up 1 V/ns, unless otherwise noted. POWER SUPPLY CURRENT AND TEMPERATURE CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
CURRENT CONSUMPTION
LVDS Configuration Min
2.375 HSTL Configuration CMOS Configuration Full Power-Down
TEMPERATURE
Ambient Temperature Range, TA
Junction Temperature, TJ −55 Typ
2.5 Max
2.625 Unit
V Test Conditions/Comments 132 148 mA 96 108 mA 156 175 mA 121 136 mA 86 96 mA 142 159 mA 118 132 mA 76 85 mA Input clock at 1200 MHz, differential mode;
all LVDS output drivers at 1200 MHz
Input clock at 800 MHz, differential mode;
all LVDS output drivers at 200 MHz
Input clock at 1200 MHz, differential mode; …