Datasheet Texas Instruments CDCE906PW

Manufacturer	Texas Instruments
Series	CDCE906
Part Number	CDCE906PW

Programmable 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP 0 to 70

Datasheets

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PDF, 1.7 Mb, Revision: H, File published: Dec 11, 2007

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Prices

Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

Packaging

Pin	20
Package Type	PW
Industry STD Term	TSSOP
JEDEC Code	R-PDSO-G
Package QTY	70
Carrier	TUBE
Device Marking	CDCE906
Width (mm)	4.4
Length (mm)	6.5
Thickness (mm)	1
Pitch (mm)	.65
Max Height (mm)	1.2
Mechanical Data	Download

Parametrics

Divider Ratio	Universal
Function	Clock Synthesizer,Clock Multiplier,Clock Divider
Input Level	Crystal,LVCMOS,Differential
Jitter-Peak to Peak(P-P) or Cycle to Cycle	60 ps C-C
Operating Temperature Range	0 to 70 C
Output Frequency(Max)	167 MHz
Output Level	LVCMOS
Output Skew	150 ps
Package Group	TSSOP
Package Size: mm2:W x L	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) PKG
Rating	Catalog
Special Features	Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC	3.3 V

Eco Plan

RoHS

Compliant

Design Kits & Evaluation Modules

Evaluation Modules & Boards: CDCE906-706PROGEVM
CDCE906 and CDCE706 programmable EVM
Lifecycle Status: Active (Recommended for new designs)
- Download
Evaluation Modules & Boards: CDCE906-706PERFEVM
CDCE906 and CDCE706 EVM
Lifecycle Status: Active (Recommended for new designs)
- Download

Application Notes

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Recommended Terminations for the Differential Inputs of CDCE906/CDCE706
PDF, 84 Kb, File published: Aug 10, 2006
This application report describes how differential signals (LVDS, LVPECL, and HSTL) can be connected to CDCE706/CDCE906 differential inputs directly. The wide common-mode voltage and smaller swing required make the devices so versatile that they can receive any signal without any complicated coupling and biasing circuits.
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CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)
PDF, 155 Kb, Revision: A, File published: Nov 28, 2007
This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs.
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High Speed Layout Guidelines (Rev. A)
PDF, 762 Kb, Revision: A, File published: Aug 8, 2017
Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection
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Clock Recommendations for the DM643x EVM
PDF, 121 Kb, File published: Nov 29, 2006
The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m
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Troubleshooting I2C Bus Protocol
PDF, 184 Kb, File published: Oct 19, 2009
When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

Model Line

Series: CDCE906 (4)

CDCE906PW CDCE906PWG4 CDCE906PWR CDCE906PWRG4

Manufacturer's Classification

Semiconductors > Clock and Timing > Clock Generators > Spread-Spectrum Clocks