Datasheet LTC3896 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 150V Low IQ, Synchronous Inverting DC/DC Controller |
| Pages / Page | 36 / 10 — pin FuncTions PLLIN (Pin 13):. TG (Pin 20):. SW (Pin 21):. BOOST (Pin … |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
pin FuncTions PLLIN (Pin 13):. TG (Pin 20):. SW (Pin 21):. BOOST (Pin 22):. BG (Pin 24):. PGOOD (Pin 14):. DRV. CC (Pin 26):
Model Line for this Datasheet
Text Version of Document
LTC3896
pin FuncTions PLLIN (Pin 13):
External Synchronization Input to Phase
TG (Pin 20):
High Current Gate Drives for Top N-Channel Detector. When an external clock is applied to this pin, MOSFET. This is the output of floating high side driver the phase-locked loop will force the rising TG signal to be with a voltage swing equal to DRVCC superimposed on synchronized with the rising edge of the external clock. If the switch node voltage SW. the MODE pin is set to Forced Continuous Mode or Burst
SW (Pin 21):
Switch Node Connection to Inductor. Mode operation, then the regulator operates in Forced Continuous Mode when synchronized. If the MODE pin is
BOOST (Pin 22):
Bootstrapped Supply to the Topside set to pulse-skipping mode, then the regulator operates Floating Driver. A capacitor is connected between the in pulse-skipping mode when synchronized. The PLLIN BOOST and SW pins. Voltage swing at the BOOST pin is pin is referenced to the GND pin, allowing the LTC3896 from approximately DRVCC to (VIN + DRVCC). to be used with a true ground-referenced external clock
BG (Pin 24):
High Current Gate Drive for Bottom source with no level shifters needed. (Synchronous) N-Channel MOSFET. Voltage swing at this
PGOOD (Pin 14):
Open-Drain Logic Output. PGOOD is pin is from V – OUT to DRVCC. pulled to GND when the voltage on the VFB pin is not within
DRV
±10% of its set point. PGOOD is referenced to GND to
CC (Pin 26):
Output of the Internal or External Low Dropout Regulators. The gate drivers are powered from this allow it to interface with external true ground-referenced voltage source. The DRV components with no level shifters needed. CC voltage is set by the DRVSET pin. Must be decoupled to V – OUT with a minimum of 4.7µF
NC (Pin 16):
No connect. Float this pin or connect to GND ceramic or other low ESR capacitor, as close as possible or V – OUT . to the IC. Do not use the DRVCC pin for any other purpose.
FREQ (Pin 17):
Frequency Control Pin for the Internal
NDRV (Pin 28):
Drive Output for External Pass Device of VCO. Connecting the pin to V – OUT forces the VCO to the NDRV LDO Linear Regulator for DRVCC. Connect this a fixed low frequency of 350kHz. Connecting the pin pin to the gate of an external NMOS pass device. To disable to INTVCC forces the VCO to a fixed high frequency of this external NDRV LDO, tie NDRV to DRVCC. 535kHz. Other frequencies between 50kHz and 900kHz
V
can be programmed by using a resistor between FREQ
IN (Pin 30):
Main Supply Pin. A bypass capacitor should be tied between this pin and the GND pin. An additional and V – OUT . An internal 20µA pull-up current develops the bypass capacitor between the V – pins is voltage to be used by the VCO to control the frequency. IN and VOUT recommended.
DRVSET (Pin 18):
DRVCC Regulation Program Pin. This
EXTV
pin sets the regulated output voltage of the DRV
CC (Pin 32):
External Power Input to an Internal LDO CC linear linear regulator Connected to DRV regulator. Tying this pin to V – CC. This LDO supplies OUT sets DRVCC to 6.0V. DRV Tying this pin to INTV CC power from EXTVCC, bypassing the internal LDO CC sets DRVCC to 10V. Other voltages powered from V between 5V and 10V can be programmed by placing a IN or the external NDRV LDO whenever EXTV resistor (50k to 100k) between the DRVSET pin and V – CC is higher than its switchover threshold (4.7V or OUT . 7.7V referenced to V – depending on the DRVUV pin). An internal 20µA pull-up current develops the voltage to OUT See the EXTV be used as the reference to the DRV CC Connection section in the Applications CC LDO. Information section. Do not exceed 14V with respect to
DRVUV (Pin 19):
DRV – CC UVLO Program Pin. This VOUT on this pin. Do not connect EXTVCC to a voltage pin determines the higher or lower DRV – CC UVLO and greater than VIN. Connect to VOUT if not used. EXTVCC switchover thresholds, as listed on the Electrical Characteristics table. Connecting DRVUV to V – OUT chooses the lower thresholds whereas tying DRVUV to INTVCC chooses the higher thresholds. Do not float this pin. 3896f 10 For more information www.linear.com/LTC3896 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
pin FuncTions PLLIN (Pin 13):
External Synchronization Input to Phase
TG (Pin 20):
High Current Gate Drives for Top N-Channel Detector. When an external clock is applied to this pin, MOSFET. This is the output of floating high side driver the phase-locked loop will force the rising TG signal to be with a voltage swing equal to DRVCC superimposed on synchronized with the rising edge of the external clock. If the switch node voltage SW. the MODE pin is set to Forced Continuous Mode or Burst
SW (Pin 21):
Switch Node Connection to Inductor. Mode operation, then the regulator operates in Forced Continuous Mode when synchronized. If the MODE pin is
BOOST (Pin 22):
Bootstrapped Supply to the Topside set to pulse-skipping mode, then the regulator operates Floating Driver. A capacitor is connected between the in pulse-skipping mode when synchronized. The PLLIN BOOST and SW pins. Voltage swing at the BOOST pin is pin is referenced to the GND pin, allowing the LTC3896 from approximately DRVCC to (VIN + DRVCC). to be used with a true ground-referenced external clock
BG (Pin 24):
High Current Gate Drive for Bottom source with no level shifters needed. (Synchronous) N-Channel MOSFET. Voltage swing at this
PGOOD (Pin 14):
Open-Drain Logic Output. PGOOD is pin is from V – OUT to DRVCC. pulled to GND when the voltage on the VFB pin is not within
DRV
±10% of its set point. PGOOD is referenced to GND to
CC (Pin 26):
Output of the Internal or External Low Dropout Regulators. The gate drivers are powered from this allow it to interface with external true ground-referenced voltage source. The DRV components with no level shifters needed. CC voltage is set by the DRVSET pin. Must be decoupled to V – OUT with a minimum of 4.7µF
NC (Pin 16):
No connect. Float this pin or connect to GND ceramic or other low ESR capacitor, as close as possible or V – OUT . to the IC. Do not use the DRVCC pin for any other purpose.
FREQ (Pin 17):
Frequency Control Pin for the Internal
NDRV (Pin 28):
Drive Output for External Pass Device of VCO. Connecting the pin to V – OUT forces the VCO to the NDRV LDO Linear Regulator for DRVCC. Connect this a fixed low frequency of 350kHz. Connecting the pin pin to the gate of an external NMOS pass device. To disable to INTVCC forces the VCO to a fixed high frequency of this external NDRV LDO, tie NDRV to DRVCC. 535kHz. Other frequencies between 50kHz and 900kHz
V
can be programmed by using a resistor between FREQ
IN (Pin 30):
Main Supply Pin. A bypass capacitor should be tied between this pin and the GND pin. An additional and V – OUT . An internal 20µA pull-up current develops the bypass capacitor between the V – pins is voltage to be used by the VCO to control the frequency. IN and VOUT recommended.
DRVSET (Pin 18):
DRVCC Regulation Program Pin. This
EXTV
pin sets the regulated output voltage of the DRV
CC (Pin 32):
External Power Input to an Internal LDO CC linear linear regulator Connected to DRV regulator. Tying this pin to V – CC. This LDO supplies OUT sets DRVCC to 6.0V. DRV Tying this pin to INTV CC power from EXTVCC, bypassing the internal LDO CC sets DRVCC to 10V. Other voltages powered from V between 5V and 10V can be programmed by placing a IN or the external NDRV LDO whenever EXTV resistor (50k to 100k) between the DRVSET pin and V – CC is higher than its switchover threshold (4.7V or OUT . 7.7V referenced to V – depending on the DRVUV pin). An internal 20µA pull-up current develops the voltage to OUT See the EXTV be used as the reference to the DRV CC Connection section in the Applications CC LDO. Information section. Do not exceed 14V with respect to
DRVUV (Pin 19):
DRV – CC UVLO Program Pin. This VOUT on this pin. Do not connect EXTVCC to a voltage pin determines the higher or lower DRV – CC UVLO and greater than VIN. Connect to VOUT if not used. EXTVCC switchover thresholds, as listed on the Electrical Characteristics table. Connecting DRVUV to V – OUT chooses the lower thresholds whereas tying DRVUV to INTVCC chooses the higher thresholds. Do not float this pin. 3896f 10 For more information www.linear.com/LTC3896 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Typical Applications Package Description Typical Application Related Parts
