Datasheet AD743 (Analog Devices) - 10

AD743 HOW CHIP PACKAGE TYPE AND POWER DISSIPATION 300 AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of the AD743 is a direct function of device junction temperature,
TA = +25 C
␪ I
JA = 165 C/W
B approximately doubling every 10°C. Figure 8 shows the rela-
200
tionship between the bias current and the junction temperature for the AD743. This graph shows that lowering the junction temperature will dramatically improve IB. ␪
JA = 115 C/W
␪
JA = 0 C/W 100 10–6 INPUT BIAS CURRENT (pA) 10–7 0 10–8 5 10 15 SUPPLY VOLTAGE ( V) TA = 25
ⴗ
C VS =
±
15V 10–9
Figure 10. Input Bias Current vs. Supply Voltage for Various Values of JA
10–10 T INPUT BIAS CURRENT (A) J 10–11
␪
A (J TO DIE MOUNT) 10–12–60 –40 –20 0 20 40 60 80 100 120 140
␪
B JUNCTION TEMPERATURE (
ⴗ
C) (DIE MOUNT TO CASE)
Figure 8. Input Bias Current vs. Junction Temperature
TA
The dc thermal properties of an IC can be closely approximated
CASE
␪ ␪ by using the simple model of Figure 9, where current represents
A + B =
␪
JC
power dissipation, voltage represents temperature, and resistors Figure 11. Breakdown of Various Package Thermal represent thermal resistance ( in °C/W). Resistances
T
␪ ␪
J JC CA REDUCED POWER SUPPLY OPERATION FOR LOWER IB
␪ Reduced power supply operation lowers I
P JA
B in two ways: first, by
IN TA
lowering both the total power dissipation and second, by reduc- ing the basic gate-to-junction leakage (Figure 10). Figure 12
P
shows a 40 dB gain piezoelectric transducer amplifier, which
IN = DEVICE DISSIPATION TA = AMBIENT TEMPERATURE
operates without an ac-coupling capacitor over the –40°C to
TJ = JUNCTION TEMPERATURE
␪ +85°C temperature range. If the optional coupling capacitor is
JC = THERMAL RESISTANCE—JUNCTION TO CASE
␪
CA = THERMAL RESISTANCE—CASE TO AMBIENT
used, this circuit will operate over the entire –55°C to +125°C military temperature range. Figure 9. Device Thermal Model
100
⍀
10k
⍀ From this model, TJ = TA + JA PIN. Therefore, IB can be deter- mined in a particular application by using Figure 8 together with
C1*
the published data for
108
⍀
** CT**
JA and power dissipation. The user can
+5V
modify JA by using of an appropriate clip-on heat sink, such as the Aavid No. 5801. JA is also a variable when using the AD743
AD743 TRANSDUCER
in chip form. Figure 10 shows the bias current versus the supply voltage with
CT 108
⍀ JA as the third variable. This graph can be used to
–5V
predict bias current after JA has been computed. Again, bias cur- rent will double for every 10°C. The designer using the AD743
*OPTIONAL DC BLOCKING CAPACITOR **OPTIONAL, SEE TEXT
in chip form (Figure 11) must also be concerned with both Figure 12. Piezoelectric Transducer JC and CA, since JC can be affected by the type of die mount technology used. Typically, JC will be in the 3°C/W to 5°C/W range; therefore, for normal packages, this small power dissipation level may be ignored. But, with a large hybrid substrate, JC will dominate proportionately more of the total JA. REV. E –9– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS CONNECTION DIAGRAMS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD SUSCEPTIBILITY ORDERING GUIDE Typical Performance Characteristics OP AMP PERFORMANCE: JFET VS. BIPOLAR DESIGNING CIRCUITS FOR LOW NOISE LOW NOISE CHARGE AMPLIFIERS HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT REDUCED POWER SUPPLY OPERATION FOR LOWER IB AN INPUT IMPEDANCE COMPENSATED, SALLEN-KEY FILTER TWO HIGH PERFORMANCE ACCELEROMETER AMPLIFIERS LOW NOISE HYDROPHONE AMPLIFIER BALANCING SOURCE IMPEDANCES OUTLINE DIMENSIONS Revision History