Datasheet LT1719 (Analog Devices) - 10

LT1719
APPLICATIONS INFORMATION
The propagation delay does not increase signifi cantly when to input feedback is kept below 4mV. However, with the driven with large differential voltages, but with low levels 2V/ns slew rate of the LT1719 outputs, a 4mV step can of overdrive, an apparent increase may be seen with large be created at a 100Ω input source with only 0.02pF of source resistances due to an RC delay caused by the 2pF output to input coupling. The LT1719’s pinout has been typical input capacitance. arranged to minimize problems by placing the sensitive inputs away from the outputs, shielded by the power rails.
Input Protection
The input and output traces of the circuit board should The input stage is protected against damage from large also be separated, and the requisite level of isolation is differential signals, up to and beyond a differential voltage readily achieved if a topside ground plane runs between equal to the supply voltage, limited only by the absolute the output and the inputs. For multilayer boards where the maximum currents noted. External input protection cir- ground plane is internal, a topside ground or supply trace cuitry is only needed if currents would otherwise exceed should be run between the inputs and the output. these absolute maximums. The internal catch diodes can Figure 2 shows a typical topside layout of the LT1719S8 conduct current up to these rated maximums without on such a multilayer board. Shown is the topside metal latchup, even when the supply voltage is at the absolute etch including traces, pin escape vias, and the land pads maximum rating. for an SO-8 LT1719 and its adjacent X7R 10nF bypass The LT1719 input stage has general purpose internal ESD capacitors in the 1206 case. The same principles should protection for the human body model. For use as a line be used with the SOT 23-6. receiver, additional external protection may be required. As with most integrated circuits, the level of immunity to ESD is much greater when residing on a printed circuit board where the power supply decoupling capacitance will limit the voltage rise caused by an ESD pulse. 1719 F02
Input Bias Current
Input bias current is measured with both inputs held at
Figure 2. Typical Topside Metal for Multilayer PCB Layouts
1V. As with any PNP differential input stage, the LT1719 bias current fl ows out of the device. It will go to zero The ground trace from Pin 5 runs under the device up on the higher of the two inputs and double on the lower to the bypass capacitor, shielding the inputs from the of the two inputs. With more than two diode drops of outputs. Note the use of a common via for the LT1719 differential input voltage, the LT1719’s input protection and the bypass capacitors, which minimizes interference circuitry activates, and current out of the lower input will from high frequency energy running around the ground increase an additional 30% and there will be a small bias plane or power distribution traces. current into the higher of the two input pins, of 4μA or less. See the Typical Performance curve Input Current vs The supply bypass should include an adjacent Differential Input Voltage. 10nF ceramic capacitor and a 2.2μF tantalum capacitor no farther than 5cm away; use more capacitance on + VS
High Speed Design Considerations
if driving more than 4mA loads. To prevent oscillations, it is helpful to balance the impedance at the inverting and Application of high speed comparators is often plagued by noninverting inputs; source impedances should be kept oscillations. The LT1719 has 4mV of internal hysteresis, low, preferably 1kΩ or less. which will prevent oscillations as long as parasitic output 1719fa 10