Datasheet LTC1293, LTC1294, LTC1296 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Single Chip 12-Bit Data Acquisition System |
| Pages / Page | 28 / 8 — BLOCK. D AGRA. (Pin numbers refer to LTC1294). TEST CIRCUITS. Load … |
| File Format / Size | PDF / 398 Kb |
| Document Language | English |
BLOCK. D AGRA. (Pin numbers refer to LTC1294). TEST CIRCUITS. Load Circuit for tdDO, tr and tf
Model Line for this Datasheet
- LTC1293BCN#PBF LTC1293BCN#PBF LTC1293BCSW#PBF LTC1293BCSW#PBF LTC1293BCSW#TRPBF LTC1293BCSW#TRPBF LTC1293CCN#PBF LTC1293CCN#PBF LTC1293CCSW#PBF LTC1293CCSW#PBF LTC1293CCSW#TRPBF LTC1293CCSW#TRPBF LTC1293DCN#PBF LTC1293DCN#PBF LTC1293DCSW#PBF LTC1293DCSW#PBF LTC1293DCSW#TRPBF LTC1293DCSW#TRPBF
- LTC1294BCN#PBF LTC1294BCN#PBF LTC1294BCSW#PBF LTC1294BCSW#PBF LTC1294BCSW#TRPBF LTC1294BCSW#TRPBF LTC1294CCN#PBF LTC1294CCN#PBF LTC1294CCSW#PBF LTC1294CCSW#PBF LTC1294CCSW#TRPBF LTC1294CCSW#TRPBF LTC1294DCN#PBF LTC1294DCN#PBF LTC1294DCSW#PBF LTC1294DCSW#PBF LTC1294DCSW#TRPBF LTC1294DCSW#TRPBF
- LTC1296BCN#PBF LTC1296BCN#PBF LTC1296BCSW#PBF LTC1296BCSW#PBF LTC1296BCSW#TRPBF LTC1296BCSW#TRPBF LTC1296BIN#PBF LTC1296BIN#PBF LTC1296BISW#PBF LTC1296BISW#PBF LTC1296BISW#TRPBF LTC1296BISW#TRPBF LTC1296CCN#PBF LTC1296CCN#PBF LTC1296CCSW#PBF LTC1296CCSW#PBF LTC1296CCSW#TRPBF LTC1296CCSW#TRPBF LTC1296CIN#PBF LTC1296CIN#PBF LTC1296CISW#PBF LTC1296CISW#PBF LTC1296CISW#TRPBF LTC1296CISW#TRPBF LTC1296DCN#PBF LTC1296DCN#PBF LTC1296DCSW#PBF LTC1296DCSW#PBF LTC1296DCSW#TRPBF LTC1296DCSW#TRPBF LTC1296DIN#PBF LTC1296DIN#PBF LTC1296DISW#PBF LTC1296DISW#PBF LTC1296DISW#TRPBF LTC1296DISW#TRPBF
Text Version of Document
LTC1293/LTC1294/LTC1296
W BLOCK I D AGRA (Pin numbers refer to LTC1294)
18 20 CLK DVCC 19 AVCC INPUT 15 OUTPUT 16 D SHIFT IN SHIFT DOUT REGISTER REGISTER 1 CH0 SAMPLE 2 CH1 AND 3 HOLD CH2 COMP 4 ANALOG CH3 5 INPUT MUX 12-BIT CH4 SAR 6 CH5 12-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM CONTROL 17 10 11 12 13 14 AND CS TIMING DGND V– AGND REF– REF+ LTC1293 BD
TEST CIRCUITS Load Circuit for tdDO, tr and tf Load Circuit for tenSSO and tdisSSO
1.4V 1.4V 3kΩ 3kΩ DOUT TEST POINT TEST POINT SSO 100pF LT1296 100pF LTC1293 TC02 LTC1293 TC08
Load Circuit for t On and Off Channel Leakage Current dis and ten
5V TEST POINT ION A ON CHANNEL 5V t 3k dis WAVEFORM 2, ten I D OFF OUT tdis WAVEFORM 1 A 100pF OFF LTC1293 TC05 CHANNELS POLARITY LTC1293 TC1 129346fs 8
W BLOCK I D AGRA (Pin numbers refer to LTC1294)
18 20 CLK DVCC 19 AVCC INPUT 15 OUTPUT 16 D SHIFT IN SHIFT DOUT REGISTER REGISTER 1 CH0 SAMPLE 2 CH1 AND 3 HOLD CH2 COMP 4 ANALOG CH3 5 INPUT MUX 12-BIT CH4 SAR 6 CH5 12-BIT 7 CH6 CAPACITIVE 8 DAC CH7 9 COM CONTROL 17 10 11 12 13 14 AND CS TIMING DGND V– AGND REF– REF+ LTC1293 BD
TEST CIRCUITS Load Circuit for tdDO, tr and tf Load Circuit for tenSSO and tdisSSO
1.4V 1.4V 3kΩ 3kΩ DOUT TEST POINT TEST POINT SSO 100pF LT1296 100pF LTC1293 TC02 LTC1293 TC08
Load Circuit for t On and Off Channel Leakage Current dis and ten
5V TEST POINT ION A ON CHANNEL 5V t 3k dis WAVEFORM 2, ten I D OFF OUT tdis WAVEFORM 1 A 100pF OFF LTC1293 TC05 CHANNELS POLARITY LTC1293 TC1 129346fs 8
