Datasheet LTC1407-1, LTC1407A-1 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown |
| Pages / Page | 26 / 9 — TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C … |
| File Format / Size | PDF / 520 Kb |
| Document Language | English |
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1). Reference Voltage. Reference Voltage vs VDD
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LTC1407-1/LTC1407A-1
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1) Reference Voltage Reference Voltage vs VDD vs Load Current
2.4902 2.4902 2.4900 2.4900 2.4898 2.4898 (V) (V) 2.4896 2.4896 REF REF V V 2.4894 2.4894 2.4892 2.4892 2.4890 2.4890 2.6 2.8 3.0 3.2 3.4 3.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD (V) LOAD CURRENT (mA) 14071 G26 14071 G27
PIN FUNCTIONS CH0+ (Pin 1):
Noninverting Channel 0. CH0+ operates the solid ground plane under the part. Keep in mind that fully differentially with respect to CH0–, with a –1.25V to analog signal currents and digital output signal currents 1.25V differential swing with respect to CH0– and a 0 to fl ow through these connections. VDD absolute input range.
VDD (Pin 7):
3V Positive Supply. This single power pin
CH0– (Pin 2):
Inverting Channel 0. CH0– operates fully supplies 3V to the entire chip. Bypass to GND pin and differentially with respect to CH0+, with a 1.25V to –1.25V solid analog ground plane with a 10μF ceramic capacitor differential swing with respect to CH0+ and a 0 to VDD (or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in absolute input range. mind that internal analog currents and digital output signal currents fl ow through this pin. Care should be taken to
VREF (Pin 3):
2.5V Internal Reference. Bypass to GND and place the 0.1μF bypass capacitor as close to Pins 6 and 7 a solid analog ground plane with a 10μF ceramic capacitor as possible. (or 10μF tantalum in parallel with 0.1μF ceramic). Can be overdriven by an external reference voltage ≥ 2.55V and
SDO (Pin 8):
Three-State Serial Data Output. Each pair of ≤VDD. output data words represent the two analog input channels at the start of the previous conversion. The output format
CH1+ (Pin 4):
Noninverting Channel 1. CH1+ operates is 2’s complement. fully differentially with respect to CH1–, with a –1.25V to 1.25V differential swing with respect to CH1– and a 0 to
SCK (Pin 9):
External Clock Input. Advances the conver- VDD absolute input range. sion process and sequences the output data on the rising edge. One or more pulses wake from sleep.
CH1– (Pin 5):
Inverting Channel 1. CH1– operates fully differentially with respect to CH1+, with a 1.25V to –1.25V
CONV (Pin 10):
Convert Start. Holds the two analog input differential swing with respect to CH1+ and a 0 to VDD signals and starts the conversion on the rising edge. Two absolute input range. pulses with SCK in fi xed high or fi xed low state starts nap mode. Four or more pulses with SCK in fi xed high or fi xed
GND (Pins 6, 11):
Ground and Exposed Pad. This single low state starts sleep mode. ground pin and the Exposed Pad must be tied directly to 14071fb 9
TYPICAL PERFORMANCE CHARACTERISTICS VDD = 3V, TA = 25°C (LTC1407-1/LTC1407A-1) Reference Voltage Reference Voltage vs VDD vs Load Current
2.4902 2.4902 2.4900 2.4900 2.4898 2.4898 (V) (V) 2.4896 2.4896 REF REF V V 2.4894 2.4894 2.4892 2.4892 2.4890 2.4890 2.6 2.8 3.0 3.2 3.4 3.6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD (V) LOAD CURRENT (mA) 14071 G26 14071 G27
PIN FUNCTIONS CH0+ (Pin 1):
Noninverting Channel 0. CH0+ operates the solid ground plane under the part. Keep in mind that fully differentially with respect to CH0–, with a –1.25V to analog signal currents and digital output signal currents 1.25V differential swing with respect to CH0– and a 0 to fl ow through these connections. VDD absolute input range.
VDD (Pin 7):
3V Positive Supply. This single power pin
CH0– (Pin 2):
Inverting Channel 0. CH0– operates fully supplies 3V to the entire chip. Bypass to GND pin and differentially with respect to CH0+, with a 1.25V to –1.25V solid analog ground plane with a 10μF ceramic capacitor differential swing with respect to CH0+ and a 0 to VDD (or 10μF tantalum) in parallel with 0.1μF ceramic. Keep in absolute input range. mind that internal analog currents and digital output signal currents fl ow through this pin. Care should be taken to
VREF (Pin 3):
2.5V Internal Reference. Bypass to GND and place the 0.1μF bypass capacitor as close to Pins 6 and 7 a solid analog ground plane with a 10μF ceramic capacitor as possible. (or 10μF tantalum in parallel with 0.1μF ceramic). Can be overdriven by an external reference voltage ≥ 2.55V and
SDO (Pin 8):
Three-State Serial Data Output. Each pair of ≤VDD. output data words represent the two analog input channels at the start of the previous conversion. The output format
CH1+ (Pin 4):
Noninverting Channel 1. CH1+ operates is 2’s complement. fully differentially with respect to CH1–, with a –1.25V to 1.25V differential swing with respect to CH1– and a 0 to
SCK (Pin 9):
External Clock Input. Advances the conver- VDD absolute input range. sion process and sequences the output data on the rising edge. One or more pulses wake from sleep.
CH1– (Pin 5):
Inverting Channel 1. CH1– operates fully differentially with respect to CH1+, with a 1.25V to –1.25V
CONV (Pin 10):
Convert Start. Holds the two analog input differential swing with respect to CH1+ and a 0 to VDD signals and starts the conversion on the rising edge. Two absolute input range. pulses with SCK in fi xed high or fi xed low state starts nap mode. Four or more pulses with SCK in fi xed high or fi xed
GND (Pins 6, 11):
Ground and Exposed Pad. This single low state starts sleep mode. ground pin and the Exposed Pad must be tied directly to 14071fb 9
