Datasheet LTC1415 (Analog Devices) - 4
| Manufacturer | Analog Devices |
| Description | 12-Bit, 1.25Msps, 55mW Sampling A/D Converter |
| Pages / Page | 24 / 4 — W U. TI I G CHARACTERISTICS (Note 5). SYMBOL. PARAMETER. CONDITIONS. MIN. … |
| File Format / Size | PDF / 338 Kb |
| Document Language | English |
W U. TI I G CHARACTERISTICS (Note 5). SYMBOL. PARAMETER. CONDITIONS. MIN. TYP. MAX. UNITS. Note 6:. Note 1:. Note 7:. Note 2:. Note 8:. Note 3:
Model Line for this Datasheet
Text Version of Document
LTC1415
W U TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 1.25 MHz Conversion and Acquisition Time ● 800 ns tCONV Conversion Time ● 700 ns tACQ Acquisition Time ● 150 ns t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 NAP/SLP↑ to SHDN↓ Setup Time (Notes 9, 10) 200 ns t4 SHDN↑ to CONVST↓ Wake-Up Time Nap Mode (Note 10) 200 ns Sleep Mode, CREFCOMP = 10µF (Note 10) 10 ms t5 CONVST Low Time (Notes 10, 11) ● 50 ns t6 CONVST to BUSY Delay CL = 25pF 10 ns ● 60 ns t7 Data Ready Before BUSY↑ 20 35 ns ● 15 ns t8 Delay Between Conversions (Note 10) ● 50 ns t9 Wait Time RD↓ After BUSY↑ (Note 10) ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 20 35 ns ● 45 ns CL = 100pF 25 45 ns ● 60 ns t11 Bus Relinquish Time 10 30 ns 0°C = TA = 70°C ● 35 ns – 40°C = TA = 85°C ● 40 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 50 ns t14 Aperture Delay of Sample-and-Hold – 1.5 ns The ● denotes specifications which apply over the full operating
Note 6:
Linearity, offset and full-scale specifications apply for a single- temperature range; all other limits and typicals TA = 25°C. ended +AIN input with – AIN grounded.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND and The deviation is measured from the center of the quantization band. AGND wired together unless otherwise noted.
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when
Note 3:
When these pin voltages are taken below ground or above V the output code flickers between 0000 0000 0000 and 1111 1111 1111. DD, they will be clamped by internal diodes. This product can handle input
Note 9:
Guaranteed by design, not subject to test. currents greater than 100mA below ground or above VDD without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below ground, they will be
Note 11:
The falling edge of CONVST starts a conversion. If CONVST clamped by internal diodes. This product can handle input currents greater returns high at a critical point during the conversion it can create small than 100mA below ground without latchup. These pins are not clamped errors. For best performance ensure that CONVST returns high either to VDD. within 425ns after the start of the conversion or after BUSY rises.
Note 5:
VDD = 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise
Note 12:
CS = RD = CONVST = 0V. specified. 4
W U TI I G CHARACTERISTICS (Note 5) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency ● 1.25 MHz Conversion and Acquisition Time ● 800 ns tCONV Conversion Time ● 700 ns tACQ Acquisition Time ● 150 ns t1 CS to RD Setup Time (Notes 9, 10) ● 0 ns t2 CS↓ to CONVST↓ Setup Time (Notes 9, 10) ● 10 ns t3 NAP/SLP↑ to SHDN↓ Setup Time (Notes 9, 10) 200 ns t4 SHDN↑ to CONVST↓ Wake-Up Time Nap Mode (Note 10) 200 ns Sleep Mode, CREFCOMP = 10µF (Note 10) 10 ms t5 CONVST Low Time (Notes 10, 11) ● 50 ns t6 CONVST to BUSY Delay CL = 25pF 10 ns ● 60 ns t7 Data Ready Before BUSY↑ 20 35 ns ● 15 ns t8 Delay Between Conversions (Note 10) ● 50 ns t9 Wait Time RD↓ After BUSY↑ (Note 10) ● – 5 ns t10 Data Access Time After RD↓ CL = 25pF 20 35 ns ● 45 ns CL = 100pF 25 45 ns ● 60 ns t11 Bus Relinquish Time 10 30 ns 0°C = TA = 70°C ● 35 ns – 40°C = TA = 85°C ● 40 ns t12 RD Low Time ● t10 ns t13 CONVST High Time ● 50 ns t14 Aperture Delay of Sample-and-Hold – 1.5 ns The ● denotes specifications which apply over the full operating
Note 6:
Linearity, offset and full-scale specifications apply for a single- temperature range; all other limits and typicals TA = 25°C. ended +AIN input with – AIN grounded.
Note 1:
Absolute Maximum Ratings are those values beyond which the life
Note 7:
Integral nonlinearity is defined as the deviation of a code from a of a device may be impaired. straight line passing through the actual endpoints of the transfer curve.
Note 2:
All voltage values are with respect to ground with DGND and The deviation is measured from the center of the quantization band. AGND wired together unless otherwise noted.
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB when
Note 3:
When these pin voltages are taken below ground or above V the output code flickers between 0000 0000 0000 and 1111 1111 1111. DD, they will be clamped by internal diodes. This product can handle input
Note 9:
Guaranteed by design, not subject to test. currents greater than 100mA below ground or above VDD without latchup.
Note 10:
Recommended operating conditions.
Note 4:
When these pin voltages are taken below ground, they will be
Note 11:
The falling edge of CONVST starts a conversion. If CONVST clamped by internal diodes. This product can handle input currents greater returns high at a critical point during the conversion it can create small than 100mA below ground without latchup. These pins are not clamped errors. For best performance ensure that CONVST returns high either to VDD. within 425ns after the start of the conversion or after BUSY rises.
Note 5:
VDD = 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise
Note 12:
CS = RD = CONVST = 0V. specified. 4
