Datasheet LTC2215, LTC2215 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | 16-Bit, 65Msps Low Noise ADC |
| Pages / Page | 36 / 1 — FEATURES. DESCRIPTION. Sample Rate: 80Msps/65Msps. 81.5dBFS Noise Floor. … |
| File Format / Size | PDF / 1.7 Mb |
| Document Language | English |
FEATURES. DESCRIPTION. Sample Rate: 80Msps/65Msps. 81.5dBFS Noise Floor. 100dB SFDR. SFDR >95dB at 70MHz. 85fsRMS Jitter
Model Line for this Datasheet
Text Version of Document
LTC2216/LTC2215 16-Bit, 80Msps/65Msps Low Noise ADC
FEATURES DESCRIPTION
n
Sample Rate: 80Msps/65Msps
The LTC®2216/LTC2215 are 80Msps/65Msps sampling 16- n
81.5dBFS Noise Floor
bit A/D converters designed for digitizing high frequency, n
100dB SFDR
wide dynamic range signals with input frequencies up to n
SFDR >95dB at 70MHz
400MHz. The input range of the ADC is fi xed at 2.75VP-P. n
85fsRMS Jitter
The LTC2216/LTC2215 are perfect for demanding com- n
2.75VP-P Input Range
munications applications, with AC performance that n
400MHz Full Power Bandwidth S/H
includes 81.5dBFS noise fl oor and 100dB spurious free n
Optional Internal Dither
dynamic range (SFDR). Ultra low jitter of 85fsRMS allows n
Optional Data Output Randomizer
undersampling of high input frequencies while maintaining n LVDS or CMOS Outputs excellent noise performance. Maximum DC specs include n Single 3.3V Supply ±3.5LSB INL, ±1LSB DNL (no missing codes). n Power Dissipation: 970mW/700mW n Clock Duty Cycle Stabilizer The digital output can be either differential LVDS or n Pin-Compatible with LTC2208, LTC2217 single-ended CMOS. There are two format options for the n 64-Pin (9mm CMOS outputs: a single bus running at the full data rate or × 9mm) QFN Package demultiplexed buses running at half data rate. A separate
APPLICATIONS
output power supply allows the CMOS output swing to range from 0.5V to 3.6V. n Telecommunications The ENC+ and ENC– inputs may be driven differentially n Receivers or single-ended with a sine wave, PECL, LVDS, TTL or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Spectrum Analysis lows high performance at full speed with a wide range of n Imaging Systems clock duty cycles. n ATE , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V SENSE
LTC2216: 64k Point FFT, fIN = 4.9MHz, –1dBFS
OV 1.575V INTERNAL ADC DD VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2μF BIAS VOLTAGE GENERATOR 1μF –10 –20 OF –30 AIN+ + CLKOUT –40 16-BIT CORRECTION OUTPUT D15 CMOS ANALOG S/H PIPELINED –50 LOGIC AND DRIVERS • OR INPUT (dBFS) AMP ADC CORE SHIFT REGISTER LVDS –60 – • AIN– • –70 D0 –80 OGND AMPLITUDE –90 –100 CLOCK/DUTY CYCLE V 3.3V DD –110 CONTROL 1μF 1μF 1μF –120 GND –130 22165 TA01 0 10 20 30 40 ENC + ENC – SHDN DITH MODE LVDS RAND FREQUENCY (MHz) 22165 TA01b ADC CONTROL INPUTS 22165f 1
FEATURES DESCRIPTION
n
Sample Rate: 80Msps/65Msps
The LTC®2216/LTC2215 are 80Msps/65Msps sampling 16- n
81.5dBFS Noise Floor
bit A/D converters designed for digitizing high frequency, n
100dB SFDR
wide dynamic range signals with input frequencies up to n
SFDR >95dB at 70MHz
400MHz. The input range of the ADC is fi xed at 2.75VP-P. n
85fsRMS Jitter
The LTC2216/LTC2215 are perfect for demanding com- n
2.75VP-P Input Range
munications applications, with AC performance that n
400MHz Full Power Bandwidth S/H
includes 81.5dBFS noise fl oor and 100dB spurious free n
Optional Internal Dither
dynamic range (SFDR). Ultra low jitter of 85fsRMS allows n
Optional Data Output Randomizer
undersampling of high input frequencies while maintaining n LVDS or CMOS Outputs excellent noise performance. Maximum DC specs include n Single 3.3V Supply ±3.5LSB INL, ±1LSB DNL (no missing codes). n Power Dissipation: 970mW/700mW n Clock Duty Cycle Stabilizer The digital output can be either differential LVDS or n Pin-Compatible with LTC2208, LTC2217 single-ended CMOS. There are two format options for the n 64-Pin (9mm CMOS outputs: a single bus running at the full data rate or × 9mm) QFN Package demultiplexed buses running at half data rate. A separate
APPLICATIONS
output power supply allows the CMOS output swing to range from 0.5V to 3.6V. n Telecommunications The ENC+ and ENC– inputs may be driven differentially n Receivers or single-ended with a sine wave, PECL, LVDS, TTL or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Spectrum Analysis lows high performance at full speed with a wide range of n Imaging Systems clock duty cycles. n ATE , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
3.3V SENSE
LTC2216: 64k Point FFT, fIN = 4.9MHz, –1dBFS
OV 1.575V INTERNAL ADC DD VCM 0.5V TO 3.6V COMMON MODE REFERENCE 0 2.2μF BIAS VOLTAGE GENERATOR 1μF –10 –20 OF –30 AIN+ + CLKOUT –40 16-BIT CORRECTION OUTPUT D15 CMOS ANALOG S/H PIPELINED –50 LOGIC AND DRIVERS • OR INPUT (dBFS) AMP ADC CORE SHIFT REGISTER LVDS –60 – • AIN– • –70 D0 –80 OGND AMPLITUDE –90 –100 CLOCK/DUTY CYCLE V 3.3V DD –110 CONTROL 1μF 1μF 1μF –120 GND –130 22165 TA01 0 10 20 30 40 ENC + ENC – SHDN DITH MODE LVDS RAND FREQUENCY (MHz) 22165 TA01b ADC CONTROL INPUTS 22165f 1
