Datasheet LTC2360, LTC2361, LTC2362 (Analog Devices) - 5

LTC2360/LTC2361/LTC2362
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) LTC2360 LTC2361 LTC2362 SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS
fSMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l 100 250 500 kHz fSCK Shift Clock Frequency (Notes 8, 9) l 10 25 50 MHz tSCK Shift Clock Period l 100 40 20 ns tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l 10 4 2 μs tACQ Acquisition Time l 2 1 0.5 μs tCONV Conversion Time l 8 3 1.5 μs t1 Minimum Positive CONV Pulse Width (Note 8) l 8 3 1.5 μs t2 SCK↑ Setup Time After CONV↓ (Note 8) l 16 16 16 ns t3 SDO Enabled Time After CONV↓ (Notes 8, 9) l 16 16 16 ns t4 SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 10) l 8 8 8 ns t5 SCK Low Time (Note 11) l 40% 40% 40% tSCK t6 SCK High Time (Note 11) l 40% 40% 40% tSCK t7 SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 10) l 4 4 4 ns t8 SDO Into Hi-Z State Time After CONV↑ (Notes 8, 9) 6 6 6 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 6:
Linearity, offset and gain specifi cations apply for a single-ended may cause permanent damage to the device. Exposure to any Absolute AIN input with respect to GND. Maximum Rating condition for extended periods may affect device
Note 7:
Typical RMS noise at code transitions. reliability and lifetime.
Note 8:
Guaranteed by characterization. All input signals are specifi ed with
Note 2:
All voltage values are with respect to GND. tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 3:
When pins AIN and VREF are taken below GND or above VDD,
Note 9:
All timing specifi cations given are with a 10pF capacitance load. they will be clamped by internal diodes. These products can handle input With a capacitance load greater than this value, a digital buffer or latch currents greater than 100mA below GND or above VDD without latch-up. must be used.
Note 4:
VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and
Note 10:
The time required for the output to cross the VIH or VIL voltage. fSCK = fSCK(MAX) unless otherwise specifi ed.
Note 11:
Guaranteed by design, not subject to test.
Note 5:
Integral linearity is defi ned as the deviation of a code from a
Note 12:
High temperatures degrade operating lifetimes. Operating lifetime straight line passing through the actual endpoints of the transfer curve. is derated at temperatures greater than 105°C. The deviation is measured from the center of the quantization band. 236012fa 5