Datasheet LTC2401, LTC2402 (Analog Devices) - 10

LTC2401/LTC2402
U U W U APPLICATIO S I FOR ATIO Converter Operation Cycle
Through timing control of the CS and SCK pins, the LTC2401/LTC2402 offer several flexible modes of opera- The LTC2401/LTC2402 are low power, delta-sigma ana- tion (internal or external SCK and free-running conversion log-to-digital converters with an easy to use 3-wire serial modes). These various modes do not require program- interface. Their operation is simple and made up of three ming configuration registers; moreover, they do not dis- states. The converter operating cycle begins with the turb the cyclic operation described above. These modes of conversion, followed by a low power sleep state and operation are described in detail in the Serial Interface concluded with the data output (see Figure 1). The 3-wire Timing Modes section. interface consists of serial data output (SDO), a serial clock (SCK) and a chip select (CS).
Conversion Clock
Initially, the LTC2401/LTC2402 perform a conversion. A major advantage delta-sigma converters offer over Once the conversion is complete, the device enters the conventional type converters is an on-chip digital filter sleep state. While in this sleep state, power consumption (commonly known as Sinc or Comb filter). For high is reduced by an order of magnitude. The part remains in resolution, low frequency applications, this filter is typi- the sleep state as long as CS is logic HIGH. The conversion cally designed to reject line frequencies of 50Hz or 60Hz result is held indefinitely in a static shift register while the plus their harmonics. In order to reject these frequencies converter is in the sleep state. in excess of 110dB, a highly accurate conversion clock is Once CS is pulled low, the device begins outputting the required. The LTC2401/LTC2402 incorporate an on-chip conversion result. There is no latency in the conversion highly accurate oscillator. This eliminates the need for result. The data output corresponds to the conversion just external frequency setting components such as crystals or performed. This result is shifted out on the serial data out oscillators. Clocked by the on-chip oscillator, the LTC2401/ pin (SDO) under the control of the serial clock (SCK). Data LTC2402 reject line frequencies (50Hz or 60Hz ±2%) a is updated on the falling edge of SCK allowing the user to minimum of 110dB. reliably latch data on the rising edge of SCK, see Figure 3. The data output state is concluded once 32 bits are read
Ease of Use
out of the ADC or when CS is brought HIGH. The device The LTC2401/LTC2402 data output has no latency, filter automatically initiates a new conversion cycle and the settling or redundant data associated with the conversion cycle repeats. cycle. There is a one-to-one correspondence between the conversion and the output data. Therefore, multiplexing an analog input voltage is easy. CONVERT The LTC2401/LTC2402 perform offset and full-scale cali- brations every conversion cycle. This calibration is trans- SLEEP parent to the user and has no effect on the cyclic operation described above. The advantage of continuous calibration is extreme stability of offset and full-scale readings with 1 CS AND respect to time, supply voltage change and temperature SCK drift. 0
Power-Up Sequence
DATA OUTPUT 24012 F01 The LTC2401/LTC2402 automatically enter an internal reset state when the power supply voltage VCC drops
Figure 1. LTC2401/LTC2402 State Transition Diagram
below approximately 2.2V. This feature guarantees the 10