Datasheet LTC2446, LTC2447 (Analog Devices) - 5
| Manufacturer | Analog Devices |
| Description | 24-Bit High Speed 8-Channel ∆Σ ADCs with Selectable Multiple Reference Inputs |
| Pages / Page | 30 / 5 — TIMING CHARACTERISTICS. The. denotes the specifications which apply over … |
| File Format / Size | PDF / 619 Kb |
| Document Language | English |
TIMING CHARACTERISTICS. The. denotes the specifications which apply over the full operating temperature
Model Line for this Datasheet
Text Version of Document
LTC2446/LTC2447
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DISCK Internal SCK Duty Cycle (Note 9) l 45 55 % fESCK External SCK Frequency Range (Note 8) l 20 MHz tLESCK External SCK Low Period (Note 8) l 25 ns tHESCK External SCK High Period (Note 8) l 25 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 41.6 35.3 30.9 µs External Oscillator (Notes 9, 10) l 320/fEOSC s tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 8) l 32/fESCK s t1 CS ↓ to SDO Low Z (Note 12) l 0 25 ns t2 CS ↑ to SDO High Z (Note 12) l 0 25 ns t3 CS ↓ to SCK ↓ (Note 9) 5 µs t4 CS ↓ to SCK ↑ (Notes 8, 12) l 25 ns tKQMAX SCK ↓ to SDO Valid l 25 ns tKQMIN SDO Hold After SCK ↓ (Note 5) l 15 ns t5 SCK Setup Before CS ↓ l 50 ns t6 SCK Hold After CS ↓ l 50 ns t7 SDI Setup Before SCK ↑ (Note 5) l 10 ns t8 SDI Hold After SCK ↑ (Note 5) l 10 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
The converter uses the internal oscillator. may cause permanent damage to the device. Exposure to any Absolute
Note 8:
The converter is in external SCK mode of operation such that the Maximum Rating condition for extended periods may affect device SCK pin is used as a digital input. The frequency of the clock signal driving reliability and lifetime. SCK during the data output is fESCK and is expressed in Hz.
Note 2:
All voltage values are with respect to GND.
Note 9:
The converter is in internal SCK mode of operation such that the
Note 3:
VCC = 4.5V to 5.5V unless otherwise specified. SCK pin is used as a digital output. In this mode of operation, the SCK pin VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; REF+ is the positive has a total equivalent load capacitance of CLOAD = 20pF. reference input, REF– is the negative reference input; VIN = IN+ – IN–,
Note 10:
The external oscillator is connected to the F V O pin. The external INCM = (IN+ + IN–)/2. oscillator frequency, fEOSC, is expressed in Hz.
Note 4:
FO pin tied to GND or to external conversion clock source with
Note 11:
The converter uses the internal oscillator. F f O = 0V. EOSC = 10MHz unless otherwise specified.
Note 12:
Guaranteed by design and test correlation.
Note 5:
Guaranteed by design, not subject to test.
Note 13:
There is an internal reset that adds an additional 5 to 15 f
Note 6:
Integral nonlinearity is defined as the deviation of a code from a O cycles to the conversion time. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
PIN FUNCTIONS GND (Pins 1, 4, 5, 6, 31, 32, 33):
Ground. Multiple ground At the conclusion of the data output state, it goes HIGH pins internally connected for optimum ground current flow indicating a new conversion has begun. and VCC decoupling. Connect each one of these pins to
EXT (Pin 3):
Internal/External SCK Selection Pin. This a common ground plane through a low impedance con- pin is used to select internal or external SCK for output- nection. All seven pins must be connected to ground for ting/inputting data. If EXT is tied low, the device is in the proper operation. external SCK mode and data is shifted out of the device
BUSY (Pin 2):
Conversion in Progress Indicator. This pin under the control of a user applied serial clock. If EXT is is HIGH while the conversion is in progress and goes LOW tied high, the internal serial clock mode is selected. The indicating the conversion is complete and data is ready. device generates its own SCK signal and outputs this on It remains LOW during the sleep and data output states. the SCK pin. A framing signal BUSY (Pin 2) goes low indicating data is being output. 24467fb For more information www.linear.com/LTC2446 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
DISCK Internal SCK Duty Cycle (Note 9) l 45 55 % fESCK External SCK Frequency Range (Note 8) l 20 MHz tLESCK External SCK Low Period (Note 8) l 25 ns tHESCK External SCK High Period (Note 8) l 25 ns tDOUT_ISCK Internal SCK 32-Bit Data Output Time Internal Oscillator (Notes 9, 11) l 41.6 35.3 30.9 µs External Oscillator (Notes 9, 10) l 320/fEOSC s tDOUT_ESCK External SCK 32-Bit Data Output Time (Note 8) l 32/fESCK s t1 CS ↓ to SDO Low Z (Note 12) l 0 25 ns t2 CS ↑ to SDO High Z (Note 12) l 0 25 ns t3 CS ↓ to SCK ↓ (Note 9) 5 µs t4 CS ↓ to SCK ↑ (Notes 8, 12) l 25 ns tKQMAX SCK ↓ to SDO Valid l 25 ns tKQMIN SDO Hold After SCK ↓ (Note 5) l 15 ns t5 SCK Setup Before CS ↓ l 50 ns t6 SCK Hold After CS ↓ l 50 ns t7 SDI Setup Before SCK ↑ (Note 5) l 10 ns t8 SDI Hold After SCK ↑ (Note 5) l 10 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
The converter uses the internal oscillator. may cause permanent damage to the device. Exposure to any Absolute
Note 8:
The converter is in external SCK mode of operation such that the Maximum Rating condition for extended periods may affect device SCK pin is used as a digital input. The frequency of the clock signal driving reliability and lifetime. SCK during the data output is fESCK and is expressed in Hz.
Note 2:
All voltage values are with respect to GND.
Note 9:
The converter is in internal SCK mode of operation such that the
Note 3:
VCC = 4.5V to 5.5V unless otherwise specified. SCK pin is used as a digital output. In this mode of operation, the SCK pin VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; REF+ is the positive has a total equivalent load capacitance of CLOAD = 20pF. reference input, REF– is the negative reference input; VIN = IN+ – IN–,
Note 10:
The external oscillator is connected to the F V O pin. The external INCM = (IN+ + IN–)/2. oscillator frequency, fEOSC, is expressed in Hz.
Note 4:
FO pin tied to GND or to external conversion clock source with
Note 11:
The converter uses the internal oscillator. F f O = 0V. EOSC = 10MHz unless otherwise specified.
Note 12:
Guaranteed by design and test correlation.
Note 5:
Guaranteed by design, not subject to test.
Note 13:
There is an internal reset that adds an additional 5 to 15 f
Note 6:
Integral nonlinearity is defined as the deviation of a code from a O cycles to the conversion time. straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
PIN FUNCTIONS GND (Pins 1, 4, 5, 6, 31, 32, 33):
Ground. Multiple ground At the conclusion of the data output state, it goes HIGH pins internally connected for optimum ground current flow indicating a new conversion has begun. and VCC decoupling. Connect each one of these pins to
EXT (Pin 3):
Internal/External SCK Selection Pin. This a common ground plane through a low impedance con- pin is used to select internal or external SCK for output- nection. All seven pins must be connected to ground for ting/inputting data. If EXT is tied low, the device is in the proper operation. external SCK mode and data is shifted out of the device
BUSY (Pin 2):
Conversion in Progress Indicator. This pin under the control of a user applied serial clock. If EXT is is HIGH while the conversion is in progress and goes LOW tied high, the internal serial clock mode is selected. The indicating the conversion is complete and data is ready. device generates its own SCK signal and outputs this on It remains LOW during the sleep and data output states. the SCK pin. A framing signal BUSY (Pin 2) goes low indicating data is being output. 24467fb For more information www.linear.com/LTC2446 5 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts
