Datasheet LT3011 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | 50mA, 3V to 80V Low Dropout Micropower Linear Regulator with PWRGD |
| Pages / Page | 16 / 10 — APPLICATIONS INFORMATION. PWRGD Flag and Timing Capacitor Delay. Figure … |
| File Format / Size | PDF / 236 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. PWRGD Flag and Timing Capacitor Delay. Figure 2. Ceramic Capacitor DC Bias Characteristics
Model Line for this Datasheet
- LT3011EDD#PBF LT3011EDD#PBF LT3011EDD#TRPBF LT3011EDD#TRPBF LT3011EMSE#PBF LT3011EMSE#PBF LT3011EMSE#TRPBF LT3011EMSE#TRPBF LT3011HMSE#PBF LT3011HMSE#PBF LT3011HMSE#TRPBF LT3011HMSE#TRPBF LT3011IDD#PBF LT3011IDD#PBF LT3011IDD#TRPBF LT3011IDD#TRPBF LT3011IMSE#PBF LT3011IMSE#PBF LT3011IMSE#TRPBF LT3011IMSE#TRPBF
Text Version of Document
LT3011
APPLICATIONS INFORMATION
in a small package, but they tend to have strong voltage
PWRGD Flag and Timing Capacitor Delay
and temperature coeffi cients, as shown in Figures 2 and 3. The PWRGD fl ag is used to indicate that the ADJ pin volt- When used with a 5V regulator, a 16V 10μF Y5V capacitor age is within 10% of the regulated voltage. The PWRGD can exhibit an effective value as low as 1μF to 2μF for the pin is an open-collector output, capable of sinking 50μA DC bias voltage applied and over the operating tempera- of current when the ADJ pin voltage is low. There is no ture range. The X5R and X7R dielectrics result in more internal pull-up on the PWRGD pin; an external pull-up stable characteristics and are more suitable for use as the resistor must be used. When the ADJ pin rises to within output capacitor. The X7R type has better stability across 10% of its fi nal reference value, a delay timer is started. temperature, while the X5R is less expensive and is avail- At the end of this delay, programmed by the value of the able in higher values. Care still must be exercised when capacitor on the CT pin, the PWRGD pin switches to a high using X5R and X7R capacitors; the X5R and X7R codes impedance and is pulled up to a logic level by an external only specify operating temperature range and maximum pull-up resistor. capacitance change over temperature. Capacitance change To calculate the capacitor value on the C due to DC bias with X5R and X7R capacitors is better than T pin, use the following formula: Y5V and Z5U capacitors, but can still be signifi cant enough I • t to drop capacitor values below appropriate levels. Capaci- C CT DELAY TIME = tor DC bias characteristics tend to improve as component V ( ) − V CT HIGH CT L ( OW) case size increases, but expected capacitance at operating voltage should be verifi ed. Figure 4 shows a block diagram of the PWRGD circuit. At start-up, the timing capacitor is discharged and the PWRGD Voltage and temperature coeffi cients are not the only pin will be held low. As the output voltage increases and sources of problems. Some ceramic capacitors have a the ADJ pin crosses the 90% threshold, the JK fl ipfl op is piezoelectric response. A piezoelectric device generates reset, and the 3μA current source begins to charge the voltage across its terminals due to mechanical stress, simi- timing capacitor. Once the voltage on the CT pin reaches lar to the way piezoelectric accelerometer or microphone the VCT(HIGH) threshold (approximately 1.7V at 25°C), the works. For a ceramic capacitor, the stress can be induced capacitor voltage is clamped and the PWRGD pin is set to by vibrations in the system or thermal transients. a high impedance state. 20 40 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10MF 20 0 X5R 0 –20 X5R –20 –40 –40 Y5V –60 CHANGE IN VALUE (%) –60 Y5V CHANGE IN VALUE (%) –80 –80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10MF –100 –100 0 2 4 6 8 10 12 14 16 –50 –25 0 25 50 75 100 125 DC BIAS VOLTAGE (V) TEMPERATURE (oC) 3011 F02 3011 F03
Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics
3011f 10
APPLICATIONS INFORMATION
in a small package, but they tend to have strong voltage
PWRGD Flag and Timing Capacitor Delay
and temperature coeffi cients, as shown in Figures 2 and 3. The PWRGD fl ag is used to indicate that the ADJ pin volt- When used with a 5V regulator, a 16V 10μF Y5V capacitor age is within 10% of the regulated voltage. The PWRGD can exhibit an effective value as low as 1μF to 2μF for the pin is an open-collector output, capable of sinking 50μA DC bias voltage applied and over the operating tempera- of current when the ADJ pin voltage is low. There is no ture range. The X5R and X7R dielectrics result in more internal pull-up on the PWRGD pin; an external pull-up stable characteristics and are more suitable for use as the resistor must be used. When the ADJ pin rises to within output capacitor. The X7R type has better stability across 10% of its fi nal reference value, a delay timer is started. temperature, while the X5R is less expensive and is avail- At the end of this delay, programmed by the value of the able in higher values. Care still must be exercised when capacitor on the CT pin, the PWRGD pin switches to a high using X5R and X7R capacitors; the X5R and X7R codes impedance and is pulled up to a logic level by an external only specify operating temperature range and maximum pull-up resistor. capacitance change over temperature. Capacitance change To calculate the capacitor value on the C due to DC bias with X5R and X7R capacitors is better than T pin, use the following formula: Y5V and Z5U capacitors, but can still be signifi cant enough I • t to drop capacitor values below appropriate levels. Capaci- C CT DELAY TIME = tor DC bias characteristics tend to improve as component V ( ) − V CT HIGH CT L ( OW) case size increases, but expected capacitance at operating voltage should be verifi ed. Figure 4 shows a block diagram of the PWRGD circuit. At start-up, the timing capacitor is discharged and the PWRGD Voltage and temperature coeffi cients are not the only pin will be held low. As the output voltage increases and sources of problems. Some ceramic capacitors have a the ADJ pin crosses the 90% threshold, the JK fl ipfl op is piezoelectric response. A piezoelectric device generates reset, and the 3μA current source begins to charge the voltage across its terminals due to mechanical stress, simi- timing capacitor. Once the voltage on the CT pin reaches lar to the way piezoelectric accelerometer or microphone the VCT(HIGH) threshold (approximately 1.7V at 25°C), the works. For a ceramic capacitor, the stress can be induced capacitor voltage is clamped and the PWRGD pin is set to by vibrations in the system or thermal transients. a high impedance state. 20 40 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10MF 20 0 X5R 0 –20 X5R –20 –40 –40 Y5V –60 CHANGE IN VALUE (%) –60 Y5V CHANGE IN VALUE (%) –80 –80 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10MF –100 –100 0 2 4 6 8 10 12 14 16 –50 –25 0 25 50 75 100 125 DC BIAS VOLTAGE (V) TEMPERATURE (oC) 3011 F02 3011 F03
Figure 2. Ceramic Capacitor DC Bias Characteristics Figure 3. Ceramic Capacitor Temperature Characteristics
3011f 10
