Datasheet LT3472 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | Boost and Inverting DC/DC Converter for CCD Bias |
| Pages / Page | 12 / 9 — APPLICATIO S I FOR ATIO. Board Layout Consideration. Figure 6. Start-Up … |
| File Format / Size | PDF / 233 Kb |
| Document Language | English |
APPLICATIO S I FOR ATIO. Board Layout Consideration. Figure 6. Start-Up Sequencing. Figure 7. Recommended Component Placement
Model Line for this Datasheet
Text Version of Document
LT3472
U U W U APPLICATIO S I FOR ATIO
the sum of the two outputs is always positive. The se- ence (EMI) problems, proper layout of the high frequency quencing is shown in Figure 6. switching path is essential. The voltage signals of the SWP and SWN pins have rise and fall times of a few ns. Minimize
Board Layout Consideration
the length and area of all traces connected to the SWP and As with all switching regulators, careful attention must be SWN pins and always use a ground plane under the paid to the PCB board layout and component placement. switching regulator to minimize interplane coupling. Rec- To maximize efficiency, switch rise and fall times are made ommended component placement is shown in Figure 7. as short as possible. To prevent electromagnetic interfer- VPOS C 5V/DIV OP CIN LP C R FBP FBP CSSP VNEG 5V/DIV LN1 VSHDN 5V/DIV CSSN 100µs/DIV 3472 FO6 C R NF FBN CFBN LN2
Figure 6. Start-Up Sequencing
CON 3472 F06
Figure 7. Recommended Component Placement
3472f 9
U U W U APPLICATIO S I FOR ATIO
the sum of the two outputs is always positive. The se- ence (EMI) problems, proper layout of the high frequency quencing is shown in Figure 6. switching path is essential. The voltage signals of the SWP and SWN pins have rise and fall times of a few ns. Minimize
Board Layout Consideration
the length and area of all traces connected to the SWP and As with all switching regulators, careful attention must be SWN pins and always use a ground plane under the paid to the PCB board layout and component placement. switching regulator to minimize interplane coupling. Rec- To maximize efficiency, switch rise and fall times are made ommended component placement is shown in Figure 7. as short as possible. To prevent electromagnetic interfer- VPOS C 5V/DIV OP CIN LP C R FBP FBP CSSP VNEG 5V/DIV LN1 VSHDN 5V/DIV CSSN 100µs/DIV 3472 FO6 C R NF FBN CFBN LN2
Figure 6. Start-Up Sequencing
CON 3472 F06
Figure 7. Recommended Component Placement
3472f 9
