Datasheet LT8415 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Ultralow Power Boost Converter with Dual Half-Bridge Switches |
| Pages / Page | 14 / 6 — PIN FUNCTIONS. SHDN (Pin 1):. VOUT (Pin 9):. CAP (Pin 10):. VCC (Pin 2):. … |
| File Format / Size | PDF / 268 Kb |
| Document Language | English |
PIN FUNCTIONS. SHDN (Pin 1):. VOUT (Pin 9):. CAP (Pin 10):. VCC (Pin 2):. VREF (Pin 11):. GND (Pin 3 and Pin 13):. SW (Pin 4):
Model Line for this Datasheet
Text Version of Document
LT8415
PIN FUNCTIONS SHDN (Pin 1):
Shutdown Pin. This pin is used to enable/
VOUT (Pin 9):
Drain of Output Disconnect PMOS. Place a disable the chip. Drive below 0.3V to disable the chip. bypass capacitor from this pin to GND. Drive above 1.4V to activate the chip. Do not float this pin.
CAP (Pin 10):
This is the Cathode of the Internal Schottky
VCC (Pin 2):
Input Supply Pin. Must be locally bypassed Diode. Place a bypass capacitor from this pin to GND. to GND. See typical applications section.
VREF (Pin 11):
Reference Pin. Soft start can be achieved by
GND (Pin 3 and Pin 13):
Ground. Tie directly to local placing a capacitor from this pin to GND. This cap will be ground plane. Pin 13 is floating but must be grounded discharged for 70µs (typical) at the beginning of start-up for proper shielding. and then be charged to 1.235V with a 10μA current source.
SW (Pin 4):
Switch Pin. This is the collector of the internal
FBP(Pin 12):
Positive Feedback Pin. This pin is the error NPN power switch. Minimize the metal trace area connected amplifier’s positive input terminal. To achieve the desired to this pin to minimize EMI. output voltage, choose the FBP pin voltage (VFBP) accord-
IN1 (Pin 5):
First Half-Bridge Control Input. Do not float ing to the following formula: this pin. VFBP = VOUT/31.85
IN2 (Pin 6):
Second Half-Bridge Control Input. Do not When resistor divider from the VREF is used to set the FBP float this pin. voltage, choose the resistor divider ratio according to the
OUT2 (Pin 7):
Second Half-Bridge Output. This pin is following formula: controlled in phase by the voltage on IN2. The output level
R1/R2 = (39.33 – VOUT)/VOUT is either the voltage on VOUT or GND. For protection purposes, the output voltage can not exceed
OUT1 (Pin 8):
First Half-Bridge Output. This pin is con- 40V even if VFBP is driven higher than VREF. trolled in phase by the voltage on IN1. The output level is either the voltage on VOUT or GND.
BLOCK DIAGRAM
VCC SHDN VOUT CAP SW OUT1 OUT2 2 1 9 10 4 8 7 ENABLE CHIP MAX VOUT 10µA 12.4M TOP GATE + 1.235V CONTROL + – OUTPUT DISCONNECT 400K CONTROL V BOTTOM GATE REF – 1.235V 11 CONTROL DISCHARGE CONTROL TIMING AND PEAK SWITCH R1 CURRENT CONTROL CONTROL VOUT TOP GATE FB – CONTROL FBP + VC 12 + 1.235V + BOTTOM GATE CONTROL R2 – 13 3 5 6 GND GND IN1 IN2 8415 BD 8415fb 6 For more information www.linear.com/LT8415
PIN FUNCTIONS SHDN (Pin 1):
Shutdown Pin. This pin is used to enable/
VOUT (Pin 9):
Drain of Output Disconnect PMOS. Place a disable the chip. Drive below 0.3V to disable the chip. bypass capacitor from this pin to GND. Drive above 1.4V to activate the chip. Do not float this pin.
CAP (Pin 10):
This is the Cathode of the Internal Schottky
VCC (Pin 2):
Input Supply Pin. Must be locally bypassed Diode. Place a bypass capacitor from this pin to GND. to GND. See typical applications section.
VREF (Pin 11):
Reference Pin. Soft start can be achieved by
GND (Pin 3 and Pin 13):
Ground. Tie directly to local placing a capacitor from this pin to GND. This cap will be ground plane. Pin 13 is floating but must be grounded discharged for 70µs (typical) at the beginning of start-up for proper shielding. and then be charged to 1.235V with a 10μA current source.
SW (Pin 4):
Switch Pin. This is the collector of the internal
FBP(Pin 12):
Positive Feedback Pin. This pin is the error NPN power switch. Minimize the metal trace area connected amplifier’s positive input terminal. To achieve the desired to this pin to minimize EMI. output voltage, choose the FBP pin voltage (VFBP) accord-
IN1 (Pin 5):
First Half-Bridge Control Input. Do not float ing to the following formula: this pin. VFBP = VOUT/31.85
IN2 (Pin 6):
Second Half-Bridge Control Input. Do not When resistor divider from the VREF is used to set the FBP float this pin. voltage, choose the resistor divider ratio according to the
OUT2 (Pin 7):
Second Half-Bridge Output. This pin is following formula: controlled in phase by the voltage on IN2. The output level
R1/R2 = (39.33 – VOUT)/VOUT is either the voltage on VOUT or GND. For protection purposes, the output voltage can not exceed
OUT1 (Pin 8):
First Half-Bridge Output. This pin is con- 40V even if VFBP is driven higher than VREF. trolled in phase by the voltage on IN1. The output level is either the voltage on VOUT or GND.
BLOCK DIAGRAM
VCC SHDN VOUT CAP SW OUT1 OUT2 2 1 9 10 4 8 7 ENABLE CHIP MAX VOUT 10µA 12.4M TOP GATE + 1.235V CONTROL + – OUTPUT DISCONNECT 400K CONTROL V BOTTOM GATE REF – 1.235V 11 CONTROL DISCHARGE CONTROL TIMING AND PEAK SWITCH R1 CURRENT CONTROL CONTROL VOUT TOP GATE FB – CONTROL FBP + VC 12 + 1.235V + BOTTOM GATE CONTROL R2 – 13 3 5 6 GND GND IN1 IN2 8415 BD 8415fb 6 For more information www.linear.com/LT8415
