Datasheet LTC3588-2 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Nanopower Energy Harvesting Power Supply with 14V Minimum VIN |
| Pages / Page | 18 / 8 — OPERATION. Internal Bridge Rectifier. Figure 1. Ideal VIN, VIN2 and CAP … |
| File Format / Size | PDF / 434 Kb |
| Document Language | English |
OPERATION. Internal Bridge Rectifier. Figure 1. Ideal VIN, VIN2 and CAP Relationship. Buck Operation
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LTC3588-2
OPERATION
The LTC3588-2 is an ultralow quiescent current power are connected to the CAP and VIN2 pins to serve as energy supply designed specifically for energy harvesting and/or reservoirs for driving the buck switches. When VIN is below low current step-down applications. The part is designed to 4.8V, VIN2 is equal to VIN and CAP is held at GND. Figure 1 interface directly to a piezoelectric or alternative A/C power shows the ideal VIN, VIN2 and CAP relationship. source, rectify a voltage waveform and store harvested 18 energy on an external capacitor, bleed off any excess power 16 via an internal shunt regulator, and maintain a regulated output voltage by means of a nanopower high efficiency 14 VIN synchronous buck regulator. 12 10
Internal Bridge Rectifier
TAGE (V) 8 VOL 6 V The LTC3588-2 has an internal full-wave bridge rectifier IN2 4 accessible via the differential PZ1 and PZ2 inputs that CAP rectifies AC inputs such as those from a piezoelectric 2 element. The rectified output is stored on a capacitor at 0 0 5 10 15 the V V IN pin and can be used as an energy reservoir for the IN (V) 35882 F01 buck converter. The low-loss bridge rectifier has a total
Figure 1. Ideal VIN, VIN2 and CAP Relationship
drop of about 400mV with typical piezo generated currents
Buck Operation
(~10µA). The bridge is capable of carrying up to 50mA. One side of the bridge can be operated as a single-ended The buck regulator uses a hysteretic voltage algorithm DC input. PZ1 and PZ2 should never be shorted together to control the output through internal feedback from the when the bridge is in use. VOUT sense pin. The buck converter charges an output capacitor through an inductor to a value slightly higher
Undervoltage Lockout (UVLO)
than the regulation point. It does this by ramping the inductor current up to 260mA through an internal PMOS When the voltage on VIN rises above the UVLO rising switch and then ramping it down to 0mA through an threshold the buck converter is enabled and charge is internal NMOS switch. This efficiently delivers energy transferred from the input capacitor to the output capacitor. to the output capacitor. The ramp rate is determined by A wide (~2V) UVLO hysteresis window allows a portion of V the energy stored on the input capacitor to be transferred IN, VOUT, and the inductor value. If the input voltage falls below the UVLO falling threshold before the output to the output capacitor by the buck. When the input capaci- voltage reaches regulation, the buck converter will shut tor voltage is depleted below the UVLO falling threshold off and will not be turned on until the input voltage again the buck converter is disabled. Extremely low quiescent rises above the UVLO rising threshold. During this time current (830nA typical, VIN = 12V) in UVLO allows energy the output voltage will be loaded by approximately 100nA. to accumulate on the input capacitor in situations where When the buck brings the output voltage into regulation energy must be harvested from low power sources. the converter enters a low quiescent current sleep state that monitors the output voltage with a sleep comparator.
Internal Rail Generation
During this operating mode load current is provided by Two internal rails, CAP and VIN2, are generated from VIN and the buck output capacitor. When the output voltage falls are used to drive the high side PMOS and low side NMOS below the regulation point the buck regulator wakes up of the buck converter, respectively. Additionally the VIN2 and the cycle repeats. This hysteretic method of providing rail serves as logic high for output voltage select bits D0 a regulated output reduces losses associated with FET and D1. The VIN2 rail is regulated at 4.8V above GND while switching and maintains an output at light loads. The buck the CAP rail is regulated at 4.8V below VIN. These are not delivers a minimum of 100mA of average current to the intended to be used as external rails. Bypass capacitors output when it is switching. 35882fc 8 For more information www.linear.com/LTC3588-2 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Revision History Typical Application Related Parts
OPERATION
The LTC3588-2 is an ultralow quiescent current power are connected to the CAP and VIN2 pins to serve as energy supply designed specifically for energy harvesting and/or reservoirs for driving the buck switches. When VIN is below low current step-down applications. The part is designed to 4.8V, VIN2 is equal to VIN and CAP is held at GND. Figure 1 interface directly to a piezoelectric or alternative A/C power shows the ideal VIN, VIN2 and CAP relationship. source, rectify a voltage waveform and store harvested 18 energy on an external capacitor, bleed off any excess power 16 via an internal shunt regulator, and maintain a regulated output voltage by means of a nanopower high efficiency 14 VIN synchronous buck regulator. 12 10
Internal Bridge Rectifier
TAGE (V) 8 VOL 6 V The LTC3588-2 has an internal full-wave bridge rectifier IN2 4 accessible via the differential PZ1 and PZ2 inputs that CAP rectifies AC inputs such as those from a piezoelectric 2 element. The rectified output is stored on a capacitor at 0 0 5 10 15 the V V IN pin and can be used as an energy reservoir for the IN (V) 35882 F01 buck converter. The low-loss bridge rectifier has a total
Figure 1. Ideal VIN, VIN2 and CAP Relationship
drop of about 400mV with typical piezo generated currents
Buck Operation
(~10µA). The bridge is capable of carrying up to 50mA. One side of the bridge can be operated as a single-ended The buck regulator uses a hysteretic voltage algorithm DC input. PZ1 and PZ2 should never be shorted together to control the output through internal feedback from the when the bridge is in use. VOUT sense pin. The buck converter charges an output capacitor through an inductor to a value slightly higher
Undervoltage Lockout (UVLO)
than the regulation point. It does this by ramping the inductor current up to 260mA through an internal PMOS When the voltage on VIN rises above the UVLO rising switch and then ramping it down to 0mA through an threshold the buck converter is enabled and charge is internal NMOS switch. This efficiently delivers energy transferred from the input capacitor to the output capacitor. to the output capacitor. The ramp rate is determined by A wide (~2V) UVLO hysteresis window allows a portion of V the energy stored on the input capacitor to be transferred IN, VOUT, and the inductor value. If the input voltage falls below the UVLO falling threshold before the output to the output capacitor by the buck. When the input capaci- voltage reaches regulation, the buck converter will shut tor voltage is depleted below the UVLO falling threshold off and will not be turned on until the input voltage again the buck converter is disabled. Extremely low quiescent rises above the UVLO rising threshold. During this time current (830nA typical, VIN = 12V) in UVLO allows energy the output voltage will be loaded by approximately 100nA. to accumulate on the input capacitor in situations where When the buck brings the output voltage into regulation energy must be harvested from low power sources. the converter enters a low quiescent current sleep state that monitors the output voltage with a sleep comparator.
Internal Rail Generation
During this operating mode load current is provided by Two internal rails, CAP and VIN2, are generated from VIN and the buck output capacitor. When the output voltage falls are used to drive the high side PMOS and low side NMOS below the regulation point the buck regulator wakes up of the buck converter, respectively. Additionally the VIN2 and the cycle repeats. This hysteretic method of providing rail serves as logic high for output voltage select bits D0 a regulated output reduces losses associated with FET and D1. The VIN2 rail is regulated at 4.8V above GND while switching and maintains an output at light loads. The buck the CAP rail is regulated at 4.8V below VIN. These are not delivers a minimum of 100mA of average current to the intended to be used as external rails. Bypass capacitors output when it is switching. 35882fc 8 For more information www.linear.com/LTC3588-2 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Revision History Typical Application Related Parts
