Datasheet AD7173-8 (Analog Devices) - 2
| Manufacturer | Analog Devices |
| Description | Low Power, 8-/16-Channel, 31.25 kSPS, 24-Bit, Highly Integrated Sigma-Delta ADC |
| Pages / Page | 64 / 2 — AD7173-8. Data Sheet. TABLE OF CONTENTS |
| Revision | B |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
AD7173-8. Data Sheet. TABLE OF CONTENTS
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AD7173-8 Data Sheet TABLE OF CONTENTS
Features .. 1 Integrated Functions .. 43 Applications ... 1 General-Purpose I/O ... 43 General Description ... 1 External Multiplexer Control ... 43 Functional Block Diagram .. 1 Delay .. 43 Revision History ... 3 16-Bit/24-Bit Conversions... 43 Specifications ... 4 Serial Interface Reset (DOUT_RESET) .. 43 Timing Characteristics .. 8 Synchronization .. 43 Absolute Maximum Ratings .. 9 Error Flags ... 44 Thermal Resistance .. 9 DATA_STAT ... 44 ESD Caution .. 9 IOSTRENGTH Bit ... 44 Pin Configuration and Function Descriptions ... 10 Grounding and Layout .. 45 Typical Performance Characteristics ... 12 Register Summary .. 46 Noise Performance and Resolution .. 18 Register Details ... 48 Getting Started .. 19 Communications Register ... 48 Power Supplies .. 20 Status Register ... 50 Digital Communication ... 20 ADC Mode Register ... 51 AD7173-8 Reset ... 21 Interface Mode Register .. 52 Configuration Overview ... 22 Register Check .. 53 Circuit Description ... 27 Data Register ... 53 Analog Input ... 27 GPIO Configuration Register ... 54 Reference Options .. 29 ID Register... 55 Clock Source ... 29 Channel Register 0 ... 55 Digital Filters ... 31 Channel Register 1 to Channel Register 15 .. 57 Sinc5 + Sinc1 Filter... 31 Setup Configuration Register 0 .. 58 Sinc3 Filter ... 32 Setup Configuration Register 1 to Setup Configuration Single Cycle Settling ... 33 Register 7 ... 59 Enhanced 50 Hz and 60 Hz Rejection Filters ... 33 Filter Configuration Register 0 ... 60 Operating Modes .. 36 Filter Configuration Register 1 to Filter Configuration Register 7 ... 61 Continuous Conversion Mode ... 36 Offset Register 0 ... 62 Continuous Read Mode ... 37 Offset Register 1 to Offset Register 7 ... 62 Single Conversion Mode ... 38 Gain Register 0.. 62 Standby and Power-Down Modes .. 39 Gain Register 1 to Gain Register 7 ... 62 Calibration Modes .. 39 Outline Dimensions ... 63 Digital Interface .. 40 Ordering Guide .. 63 Checksum Protection... 40 CRC Calculation ... 41
Rev. B | Page 2 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
AD7173-8 Data Sheet TABLE OF CONTENTS
Features .. 1 Integrated Functions .. 43 Applications ... 1 General-Purpose I/O ... 43 General Description ... 1 External Multiplexer Control ... 43 Functional Block Diagram .. 1 Delay .. 43 Revision History ... 3 16-Bit/24-Bit Conversions... 43 Specifications ... 4 Serial Interface Reset (DOUT_RESET) .. 43 Timing Characteristics .. 8 Synchronization .. 43 Absolute Maximum Ratings .. 9 Error Flags ... 44 Thermal Resistance .. 9 DATA_STAT ... 44 ESD Caution .. 9 IOSTRENGTH Bit ... 44 Pin Configuration and Function Descriptions ... 10 Grounding and Layout .. 45 Typical Performance Characteristics ... 12 Register Summary .. 46 Noise Performance and Resolution .. 18 Register Details ... 48 Getting Started .. 19 Communications Register ... 48 Power Supplies .. 20 Status Register ... 50 Digital Communication ... 20 ADC Mode Register ... 51 AD7173-8 Reset ... 21 Interface Mode Register .. 52 Configuration Overview ... 22 Register Check .. 53 Circuit Description ... 27 Data Register ... 53 Analog Input ... 27 GPIO Configuration Register ... 54 Reference Options .. 29 ID Register... 55 Clock Source ... 29 Channel Register 0 ... 55 Digital Filters ... 31 Channel Register 1 to Channel Register 15 .. 57 Sinc5 + Sinc1 Filter... 31 Setup Configuration Register 0 .. 58 Sinc3 Filter ... 32 Setup Configuration Register 1 to Setup Configuration Single Cycle Settling ... 33 Register 7 ... 59 Enhanced 50 Hz and 60 Hz Rejection Filters ... 33 Filter Configuration Register 0 ... 60 Operating Modes .. 36 Filter Configuration Register 1 to Filter Configuration Register 7 ... 61 Continuous Conversion Mode ... 36 Offset Register 0 ... 62 Continuous Read Mode ... 37 Offset Register 1 to Offset Register 7 ... 62 Single Conversion Mode ... 38 Gain Register 0.. 62 Standby and Power-Down Modes .. 39 Gain Register 1 to Gain Register 7 ... 62 Calibration Modes .. 39 Outline Dimensions ... 63 Digital Interface .. 40 Ordering Guide .. 63 Checksum Protection... 40 CRC Calculation ... 41
Rev. B | Page 2 of 64 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES Single Supply Operation (AVSS = DGND) Split Supply Operation (AVSS ≠ DGND) DIGITAL COMMUNICATION Accessing the ADC Register Map AD7173-8 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Buffered Analog Input Fully Differential Inputs Single-Ended Inputs Buffer Chopping, Noise, and Input Current Running with Single Cycle = 0 Using External Buffers REFERENCE OPTIONS External Reference Internal Reference CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS 50 Hz and 60 Hz Rejection Filter Frequency Domain Plots OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR /ERROR Pin DATA_STAT IOSTRENGTH BIT GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE NOTES
