Datasheet AD7787 (Analog Devices) - 5

ManufacturerAnalog Devices
DescriptionLow Power, 2-Channel 24-Bit Sigma-Delta ADC
Pages / Page21 / 5 — AD7787. Data Sheet. Parameter. AD7787B. Unit. Test Conditions/Comments
RevisionA
File Format / SizePDF / 364 Kb
Document LanguageEnglish

AD7787. Data Sheet. Parameter. AD7787B. Unit. Test Conditions/Comments

AD7787 Data Sheet Parameter AD7787B Unit Test Conditions/Comments

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AD7787 Data Sheet Parameter AD7787B Unit Test Conditions/Comments
LOGIC INPUTS All Inputs Except SCLK1 VINL, Input Low Voltage 0.8 V max VDD = 5 V. 0.4 V max VDD = 3 V. VINH, Input High Voltage 2.0 V min VDD = 3 V or 5 V. SCLK Only (Schmitt-Triggered Input)1 VT(+) 1.4/2 V min/V max VDD = 5 V. VT(−) 0.8/1.4 V min/V max VDD = 5 V. VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 5 V. VT(+) 0.9/2 V min/V max VDD = 3 V. VT(−) 0.4/1.1 V min/V max VDD = 3 V. VT(+) − VT(−) 0.3/0.85 V min/V max VDD = 3 V. Input Currents ±1 µA max VIN = VDD or GND. Input Capacitance 10 pF typ All Digital Inputs. LOGIC OUTPUTS VOH, Output High Voltage1 VDD − 0.6 V min VDD = 3 V, ISOURCE = 100 µA. VOL, Output Low Voltage1 0.4 V max VDD = 3 V, ISINK = 100 µA. VOH, Output High Voltage1 4 V min VDD = 5 V, ISOURCE = 200 µA. VOL, Output Low Voltage1 0.4 V max VDD = 5 V, ISINK = 1.6 mA. Floating-State Leakage Current ±1 µA max Floating-State Output Capacitance 10 pF typ Data Output Coding Offset Binary POWER REQUIREMENTS5 Power Supply Voltage VDD − GND 2.5/5.25 V min/max Power Supply Currents IDD Current6 75 µA max 65 µA typ, VDD = 3.6 V, unbuffered mode. 145 µA max 130 µA typ, VDD = 3.6 V, buffered mode. 80 µA max 73 µA typ, VDD = 5.25 V, unbuffered mode. 160 µA max 145 µA typ, VDD = 5.25 V, buffered mode. IDD (Power-Down Mode) 1 µA max 1 Specification is not production tested but is supported by characterization data at initial product release. 2 Full-scale error applies to both positive and negative full scale and applies at the factory calibration conditions (VDD = 4 V). 3 The AD7787 can tolerate absolute analog input voltages down to GND − 200 mV but the leakage current will increase. 4 FS[2:0] are the three bits used in the filter register to select the output word rate. 5 Digital inputs equal to VDD or GND. 6 The current consumption can be further reduced by using the ADC in one of the low power modes (see Table 14). Rev. A | Page 4 of 20 Document Outline Specifications Timing Characteristics Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics On-Chip Registers Communications Register (RS1, RS0 = 0, 0) Status Register (RS1, RS0 = 0, 0; Power-On/Reset = 0×8C) Mode Register (RS1, RS0 = 0, 1; Power-On/Reset = 0×02) Filter Register (RS1, RS0 = 1, 0; Power-On/Reset = 0×04) Data Register (RS1, RS0 = 1, 1; Power-On/Reset = 0×000000) ADC Circuit Information Overview Noise Performance Reduced Current Modes Digital Interface Single Conversion Mode Continuous Conversion Mode Continuous Read Mode Circuit Description Analog Input Channel Bipolar/Unipolar Configuration Data Output Coding Reference Input VDD Monitor Grounding and Layout Applications Battery Monitoring Outline Dimensions Ordering Guide
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