Datasheet AD7452 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | Differential Input, 555 kSPS, 12-Bit A/D Converter in 8-Lead SOT-23 |
| Pages / Page | 25 / 8 — Data Sheet. AD7452. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VDD 1. … |
| Revision | C |
| File Format / Size | PDF / 648 Kb |
| Document Language | English |
Data Sheet. AD7452. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VDD 1. VREF. SCLK. VIN+. SDATA. TOP VIEW. VIN–. (Not to Scale). GND
Model Line for this Datasheet
Text Version of Document
link to page 19
Data Sheet AD7452 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 8 VREF SCLK 2 AD7452 7 VIN+ SDATA 3 TOP VIEW 6 VIN– (Not to Scale) CS 4 5 GND
03154-A-004 Figure 4. 8-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions Mnemonic Function
V Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is REF 2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details. V Positive Terminal for Differential Analog Input. IN+ V Negative Terminal for Differential Analog Input. IN– GND Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference signal should be referred to this GND voltage. CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and framing the serial data transfer. SDATA Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first. The output coding is twos complement. SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. V Power Supply Input. V is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor DD DD and a 10 µF tantalum capacitor in parallel. Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE APPLICATION HINTS Grounding and Layout EVALUATING THE AD7452’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7452 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VDD 1 8 VREF SCLK 2 AD7452 7 VIN+ SDATA 3 TOP VIEW 6 VIN– (Not to Scale) CS 4 5 GND
03154-A-004 Figure 4. 8-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions Mnemonic Function
V Reference Input for the AD7452. An external reference must be applied to this input. For a 5 V power supply, the reference is REF 2.5 V (± 1%) for specified performance. For a 3 V power supply, the reference is 2 V (± 1%) for specified performance. This pin should be decoupled to GND with a capacitor of at least 0.1 µF. See the Reference section for more details. V Positive Terminal for Differential Analog Input. IN+ V Negative Terminal for Differential Analog Input. IN– GND Analog Ground. Ground reference point for all circuitry on the AD7452. All analog input signals and any external reference signal should be referred to this GND voltage. CS Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7452 and framing the serial data transfer. SDATA Serial Data. Logic output. The conversion result from the AD7452 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data, which are provided MSB first. The output coding is twos complement. SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process. V Power Supply Input. V is 3 V (+20%/–10%) or 5 V (± 5%). This supply should be decoupled to GND with a 0.1 µF capacitor DD DD and a 10 µF tantalum capacitor in parallel. Rev. C | Page 7 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS CIRCUIT INFORMATION CONVERTER OPERATION ADC TRANSFER FUNCTION TYPICAL CONNECTION DIAGRAM ANALOG INPUT Analog Input Structure DRIVING DIFFERENTIAL INPUTS Differential Amplifier Op Amp Pair RF Transformer DIGITAL INPUTS REFERENCE Example 1 Example 2 SINGLE-ENDED OPERATION SERIAL INTERFACE Timing Example MODES OF OPERATION NORMAL MODE POWER-DOWN MODE POWER-UP TIME POWER vs. THROUGHPUT RATE APPLICATION HINTS Grounding and Layout EVALUATING THE AD7452’S PERFORMANCE OUTLINE DIMENSIONS ORDERING GUIDE
