Datasheet AD7738 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 8-Channel, 8.5 kHz, 24-Bit Sigma-Delta A/D Converter |
| Pages / Page | 29 / 6 — AD7738. SCLK. DOUT. MSB. LSB. t14. t15. t13. DIN. ISINK (800. A AT DVDD = … |
| File Format / Size | PDF / 422 Kb |
| Document Language | English |
AD7738. SCLK. DOUT. MSB. LSB. t14. t15. t13. DIN. ISINK (800. A AT DVDD = 5V 100. A AT DVDD = 3V). OUTPUT. 1.6V. PIN. 50pF. ISOURCE ( 200
Model Line for this Datasheet
Text Version of Document
AD7738 CS t t 4 t 8 6 SCLK t7 t5 t t9 5A DOUT MSB LSB
Figure 1. Read Cycle Timing Diagram
CS t t 11 16 t14 SCLK t t15 12 t13 DIN MSB LSB
Figure 2. Write Cycle Timing Diagram
ISINK (800 A AT DVDD = 5V 100 A AT DVDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE ( 200 A AT DVDD = 5V 100 A AT DVDD = 3V)
Figure 3. Load Circuit for Access Time and Bus Relinquish Time REV. 0 –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS
Figure 1. Read Cycle Timing Diagram
CS t t 11 16 t14 SCLK t t15 12 t13 DIN MSB LSB
Figure 2. Write Cycle Timing Diagram
ISINK (800 A AT DVDD = 5V 100 A AT DVDD = 3V) TO OUTPUT 1.6V PIN 50pF ISOURCE ( 200 A AT DVDD = 5V 100 A AT DVDD = 3V)
Figure 3. Load Circuit for Access Time and Bus Relinquish Time REV. 0 –5– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION PIN FUNCTION DESCRIPTION (continued) OUTPUT NOISE AND RESOLUTION SPECIFICATION CHOPPING ENABLED CHOPPING DISABLED Typical Performance Characteristics REGISTER DESCRIPTION Communications Register I/O Port Register Revision Register Test Register ADC Status Register Checksum Register ADC Zero Scale Calibration Register ADC Full-Scale Register Channel Data Registers Channel Zero-Scale Calibration Registers Channel Full-Scale Calibration Registers Channel Status Registers Channel Setup Registers Channel Conversion Time Registers Mode Register DIGITAL INTERFACE DESCRIPTION Hardware Reset Access the AD7738 Registers Single Conversion and Reading Data Dump Mode Continuous Conversion Mode Continuous Read (Continuous Conversion) Mode CIRCUIT DESCRIPTION Analog Front End Sigma-Delta ADC Chopping Multiplexer, Conversion, and Data Output Timing Frequency Response Analog Inputs Voltage Range Analog Inputs Extended Voltage Range Voltage Reference Inputs Reference Detect I/O Port CALIBRATION ADC Zero-Scale Self-Calibration Per Channel System Calibration OUTLINE DIMENSIONS
