Datasheet AD7720 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | CMOS Sigma-Delta Modulator with 90 dB Dynamic Range |
| Pages / Page | 17 / 3 — AD7720–SPECIFICATIONS1 (AVDD = +5 V. 5%; DVDD = +5 V. 5%; AGND = DGND = 0 … |
| File Format / Size | PDF / 271 Kb |
| Document Language | English |
AD7720–SPECIFICATIONS1 (AVDD = +5 V. 5%; DVDD = +5 V. 5%; AGND = DGND = 0 V, fMCLK = 12.5 MHz,
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AD7720–SPECIFICATIONS1 (AVDD = +5 V
6
5%; DVDD = +5 V
6
5%; AGND = DGND = 0 V, fMCLK = 12.5 MHz, REF2 = +2.5 V; TA = TMIN to TMIN, unless otherwise noted) Parameter B Version Units Test Conditions/Comments
STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1 Resolution 16 Bits Differential Nonlinearity ±1 LSB max Guaranteed Monotonic Integral Nonlinearity ±2 LSB typ Precalibration Offset Error ±6 mV typ Precalibration Gain Error2 ±0.6 % FSR typ Postcalibration Offset Error3 ±1.5 mV typ Postcalibration Gain Error2, 3 ±0.3 % FSR typ Offset Error Drift ±1 LSB/°C typ Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode ±1 LSB/°C typ Bipolar Mode ±0.5 LSB/°C typ ANALOG INPUTS Signal Input Span (VIN(+) – VIN(–)) Bipolar Mode ±VREF2/2 V max BIP = VIH Unipolar Mode 0 to VREF2 V max BIP = VIL Maximum Input Voltage AVDD V Minimum Input Voltage 0 V Input Sampling Capacitance 2 pF typ Input Sampling Rate 2 fMCLK MHz Differential Input Impedance 109/(8 fMCLK) kΩ typ REFERENCE INPUTS REF1 Output Voltage 2.32 to 2.62 V min/max REF1 Output Voltage Drift 60 ppm/°C typ REF1 Output Impedance 3 kΩ typ Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2 Using Internal Reference REF2 Output Voltage 2.32 to 2.62 V min/max REF2 Output Voltage Drift 60 ppm/°C typ Using External Reference REF1 = AGND REF2 Input Impedance 109/(16 fMCLK) kΩ typ External Reference Voltage Range 2.32 to 2.62 V min/max Applied to REF1 or REF2 DYNAMIC SPECIFICATIONS4 When Tested with Ideal FIR Filter as in Figure 1 Bipolar Mode BIP = VIH, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V Signal to (Noise + Distortion)5 90 dB typ Input BW = 0 kHz–90.625 kHz 86/84.5 dB min Total Harmonic Distortion5 –90/–88 dB max Input BW = 0 kHz–90.625 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–90.625 kHz Unipolar Mode BIP = VIL, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V Signal to (Noise + Distortion)5 88 dB typ Input BW = 0 kHz–90.625 kHz 84.5/83 dB min Total Harmonic Distortion5 –89/–87 dB max Input BW = 0 kHz–97.65 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–97.65 kHz Intermodulation Distortion –93 dB typ AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, VCM = 1.25 V to 3.75 V, 20 kHz Overall Digital Filter Response See Figure 1 for Characteristics of FIR Filter 0 kHz–90.625 kHz ±0.005 dB max 96.92 kHz –3 dB min 104.6875 kHz to 12.395 MHz 90 dB typ CLOCK MCLK Duty Ratio 45 to 55 % max For Specified Operation VMCLKH, MCLK High Voltage 4 V min MCLK Uses CMOS Logic VMCLKL, MCLK Low Voltage 0.4 V max –2– REV. 0
6
5%; DVDD = +5 V
6
5%; AGND = DGND = 0 V, fMCLK = 12.5 MHz, REF2 = +2.5 V; TA = TMIN to TMIN, unless otherwise noted) Parameter B Version Units Test Conditions/Comments
STATIC PERFORMANCE When Tested with Ideal FIR Filter as in Figure 1 Resolution 16 Bits Differential Nonlinearity ±1 LSB max Guaranteed Monotonic Integral Nonlinearity ±2 LSB typ Precalibration Offset Error ±6 mV typ Precalibration Gain Error2 ±0.6 % FSR typ Postcalibration Offset Error3 ±1.5 mV typ Postcalibration Gain Error2, 3 ±0.3 % FSR typ Offset Error Drift ±1 LSB/°C typ Gain Error Drift REF2 Is an Ideal Reference, REF1 = AGND Unipolar Mode ±1 LSB/°C typ Bipolar Mode ±0.5 LSB/°C typ ANALOG INPUTS Signal Input Span (VIN(+) – VIN(–)) Bipolar Mode ±VREF2/2 V max BIP = VIH Unipolar Mode 0 to VREF2 V max BIP = VIL Maximum Input Voltage AVDD V Minimum Input Voltage 0 V Input Sampling Capacitance 2 pF typ Input Sampling Rate 2 fMCLK MHz Differential Input Impedance 109/(8 fMCLK) kΩ typ REFERENCE INPUTS REF1 Output Voltage 2.32 to 2.62 V min/max REF1 Output Voltage Drift 60 ppm/°C typ REF1 Output Impedance 3 kΩ typ Reference Buffer Offset Voltage ±12 mV max Offset Between REF1 and REF2 Using Internal Reference REF2 Output Voltage 2.32 to 2.62 V min/max REF2 Output Voltage Drift 60 ppm/°C typ Using External Reference REF1 = AGND REF2 Input Impedance 109/(16 fMCLK) kΩ typ External Reference Voltage Range 2.32 to 2.62 V min/max Applied to REF1 or REF2 DYNAMIC SPECIFICATIONS4 When Tested with Ideal FIR Filter as in Figure 1 Bipolar Mode BIP = VIH, VCM = 2.5 V, VIN(+) = VIN(–) = 1.25 V p-p or VIN(–) = 1.25 V, VIN(+) = 0 V to 2.5 V Signal to (Noise + Distortion)5 90 dB typ Input BW = 0 kHz–90.625 kHz 86/84.5 dB min Total Harmonic Distortion5 –90/–88 dB max Input BW = 0 kHz–90.625 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–90.625 kHz Unipolar Mode BIP = VIL, VIN(–) = 0 V, VIN(+) = 0 V to 2.5 V Signal to (Noise + Distortion)5 88 dB typ Input BW = 0 kHz–90.625 kHz 84.5/83 dB min Total Harmonic Distortion5 –89/–87 dB max Input BW = 0 kHz–97.65 kHz Spurious Free Dynamic Range –90 dB max Input BW = 0 kHz–97.65 kHz Intermodulation Distortion –93 dB typ AC CMRR 96 dB typ VIN(+) = VIN(–) = 2.5 V p-p, VCM = 1.25 V to 3.75 V, 20 kHz Overall Digital Filter Response See Figure 1 for Characteristics of FIR Filter 0 kHz–90.625 kHz ±0.005 dB max 96.92 kHz –3 dB min 104.6875 kHz to 12.395 MHz 90 dB typ CLOCK MCLK Duty Ratio 45 to 55 % max For Specified Operation VMCLKH, MCLK High Voltage 4 V min MCLK Uses CMOS Logic VMCLKL, MCLK Low Voltage 0.4 V max –2– REV. 0
