Datasheet AD7874 (Analog Devices) - 5

AD7874 TERMINOLOGY PIN CONFIGURATIONS ACQUISITION TIME
Acquisition Time is the time required for the output of the
DIP and SOIC
track/hold amplifiers to reach their final values, within ± 1/2 LSB, after the falling edge of INT (the point at which the track/ holds return to track mode). This includes switch delay time,
V 1 28 V IN1 IN4
slewing time and settling time for a full-scale voltage change.
V 2 27 V IN2 IN3 V 3 26 V DD SS APERTURE DELAY INT 4 25 REF OUT
Aperture Delay is defined as the time required by the internal
CONVST 5 24 REF IN
switches to disconnect the hold capacitors from the inputs. This
RD 6 23 AGND
produces an effective delay in sample timing. It is measured by
AD7874 CS 7 22 DB0 (LSB)
applying a step input and adjusting the CONVST input position
TOP VIEW CLK 8 21 DB1
until the output code follows the step input change.
(Not to Scale) V 9 20 DB2 DD APERTURE DELAY MATCHING DB11 (MSB) 10 19 DB3
Aperture Delay Matching is the maximum deviation in aperture
DB10 11 18 DB4
delays across the four on-chip track/hold amplifiers.
DB9 12 17 DB5 DB8 13 16 DB6 APERTURE JITTER DGND 14 15 DB7
Aperture Jitter is the uncertainty in aperture delay caused by internal noise and variation of switching thresholds with signal level.
LCCC DROOP RATE DD IN2 IN1 IN4 IN3 SS INT V V V V V V
Droop Rate is the change in the held analog voltage resulting
4 3 2 1 28 27 26
from leakage currents.
CONVST 5 25 REF OUT CHANNEL-TO-CHANNEL ISOLATION RD 6 24 REF IN CS 7 AD7874
Channel-to-Channel Isolation is a measure of the level of
23 AGND TOP VIEW
crosstalk between channels. It is measured by applying a full-
CLK 8 22 DB0 (LSB) (Not to Scale) 9 21
scale 1 kHz signal to the other three inputs. The figure given is
V DB1 DD DB11 (MSB) 10 20 DB2
the worst case across all four channels.
DB10 11 19 DB3 SNR, THD, IMD 12 13 14 15 16 17 18
See DYNAMIC SPECIFICATIONS section.
DB9 DB8 DB7 DB6 DB5 DB4 DGND
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